MAC7200 datasheet(294/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

216

Freescale Semiconductor

12.2.4.1.7

DMA Set Enable Error Interrupt (DMASEEI)

The DMASEEI register provides a simple memory-mapped mechanism to set a given bit in the

DMAEEI{H,L} registers to enable the error interrupt for a given channel. The data value on a register

write causes the corresponding bit in the DMAEEI{H,L} register to be set. A data value of 64 to 127

(regardless of the number of implemented channels) provides a global set function, forcing the entire

contents of DMAEEI{H,L} to be asserted. Reads of this register return all zeroes. See Figure 12-8 and

Table 12-11 for the DMASEEI definition.

76543210

00000000

CERQ[6:0]

Reset

0000000

= Unimplemented

Figure 12-7. DMA Clear Enable Request (DMACERQ) Register

Table 12-10. DMACERQ Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

CERQ[6:0]

Clear Enable Request

0-63

Clear corresponding bit in DMAERQ{H,L}

64-127 Clear all bits in DMAERQ{H,L}

76543210

00000000

SEEI[6:0]

Reset

0000000

= Unimplemented

Figure 12-8. DMA Set Enable Error Interrupt (DMASEEI) Register

Table 12-11. DMASEEI Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

SEEI[6:0]

Set Enable Error Interrupt.

0-63

Set the corresponding bit in DMAEEI{H,L}

64-127 Set all bits in DMAEEI{H,L}

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