MAC7200 datasheet(296/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

218

Freescale Semiconductor

12.2.4.1.10

DMA Clear Error (DMACERR)

The DMACEER register provides a simple memory-mapped mechanism to clear a given bit in the

DMAERR{H,L} registers to disable the error condition flag for a given channel. The given value on a

64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the

entire contents of the DMAERR{H,L} to be zeroed, clearing all channel error indicators. Reads of this

12.2.4.1.11

DMA Set START Bit (DMASSRT)

The DMASSRT register provides a simple memory-mapped mechanism to set the START bit in the TCD

of the given channel. The data value on a register write causes the START bit in the corresponding Transfer

Control Descriptor to be set. A data value of 64 to 127 (regardless of the number of implemented channels)

provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. See

Table 12-28 for the TCD START bit definition.

Table 12-13. DMACINT Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

CINT[6:0]

Clear Interrupt Request.

0-63

Clear the corresponding bit in DMAINT{H,L}

64-127 Clear all bits in DMAINT{H,L}

76543210

00000000

CERR[6:0]

Reset

0000000

= Unimplemented

Figure 12-11. DMA Clear Error (DMACERR) Register

Table 12-14. DMACERR Field Descriptions

Field

Description

Reserved, should be cleared.

6–0

CERR[6:0]

Clear Error Indicator.

0-63

Clear corresponding bit in DMAERR{H,L}

64-127 Clear all bits in DMAERR{H,L}

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