MAC7200 datasheet(299/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

221

12.2.4.1.14

DMA Error (DMAERRH, DMAERRL)

The DMAERR{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the

presence of an error for each channel. DMAERRH supports channels 63-32, while DMAERRL covers

channels 31-00. The dma_engine signals the occurrence of a error condition by setting the appropriate bit

in this register. The outputs of this register are enabled by the contents of the DMAEEI register, then

logically summed across groups of 16, 32 and 64 channels to form several group error interrupt requests

which is then routed to the platform’s interrupt controller. During the execution of the interrupt service

routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating

the error interrupt request. Typically, a write to the DMACERR register in the interrupt service routine is

used for this purpose. Recall the normal DMA channel completion indicators, setting the transfer control

descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is

detected.

The contents of this register can also be polled and a non-zero value indicates the presence of a channel

error, regardless of the state of the DMAEEI register. The state of any given channel’s error indicators is

affected by writes to this register; it is also affected by writes to the DMACERR register. On writes to the

DMAERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit

position has no affect on the corresponding channel’s current error status. The DMACERR register is

provided so the error indicator for a single channel can easily be cleared. See Figure 12-15 and Table 12-18

for the DMAERR definition.

Table 12-17. DMAINTH, DMAINTL Field Descriptions

Field

Description

31–16

Reserved, should be cleared.

15–0

INTn,

n = 0,... 15

DMA Interrupt Request n.

0 The interrupt request for channel n is cleared.

1 The interrupt request for channel n is active.

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