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MAC7200 Datasheet(PDF) 291 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 291 Page - Freescale Semiconductor, Inc |
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291 / 976 page  The SPP DMA Controller Module (SPP_DMA2) MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 213 the request enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the DMAERQ{H,L} registers. Both the DMA request input signal and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. See Figure 12-4 and Table 12-7 for the DMAERQ definition. As a given channel completes the processing of its major iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the DMAERQ bit for that channel. If the TCD.d_req Register address: DMA_Offset + 0x0008 (DMAERQH) + 0x000c (DMAERQL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000000000000000 W Reset 0000000000000000 15 14 13 12 11 10 9876543210 R 0000000000000000 W Reset 0000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0000000000000000 W Reset 0000000000000000 15 14 13 12 11 10 9876543210 R W Reset 0000000000000000 Figure 12-4. DMA Enable Request (DMAERQH, DMAERQL) Register Table 12-7. DMAERQH, DMAERQL field Descriptions Field Description 31–16 Reserved, should be cleared. 15–0 ERQn n = 0,... 15 Enable DMA Request n. 0 The DMA request signal for channel n is disabled. 1 The DMA request signal for channel n is enabled. |
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