MAC7200 datasheet(288/976 Pages) FREESCALE

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The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

210

Freescale Semiconductor

12.2.4.1.2

DMA Error Status (DMAES)

The DMAES register provides information concerning the last recorded channel error. Channel errors can

be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority

A configuration error is caused when the starting source or destination address, source or destination

offsets, minor loop byte count and the transfer size represent an inconsistent state. The addresses and

offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a

multiple of the source and destination transfer sizes. All source reads and destination writes must be

configured to the natural boundary of the programmed transfer size respectively. In fixed arbitration mode,

a configuration error is caused by any two channel priorities being equal. All channel priority levels must

be unique when fixed arbitration mode is enabled. If a scatter/gather operation is enabled upon channel

completion, a configuration error is reported if the scatter/gather address (dlast_sga) is not aligned on a

000000000000000

Reset

9876543210

0000000000000

Reset

= Unimplemented

Figure 12-2. DMA Control Register (DMACR)

Table 12-5. DMACR Field Descriptions

Field

Description

31–3

Reserved, should be cleared.

ERCA

Enable Round Robin Channel Arbitration.

0 Fixed priority arbitration is used for channel selection.

1 Round robin arbitration is used for channel selection.

EDBG

Enable Debug.

0 The assertion of the ipg_debug input is ignored.

1 The assertion of the ipg_debug input causes the DMA to stall the start of a new channel. Executing channels are

allowed to complete. Channel execution will resume when either the ipg_debug input is negated or the EDBG bit

is cleared.

EBW

Enable Buffered Writes.

0 The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes.

1 The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the last write sequence.

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