ADS8331

ADS8332

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SBAS363 – DECEMBER 2009

READING THE CONVERSION RESULT

The conversion result is available to the input of the output data register (ODR) at EOC and presented to the

output of the output register at the next falling edge of FS/CS. The host processor can then shift the data out via

the SDO pin at any time except during the quiet zone. This duration is 20ns before and 20ns after the end of

sampling (EOS) period. End of sampling (EOS) is defined as the falling edge of CONVST when Manual-Trigger

mode is used or the end of the third conversion clock (CCLK) after EOC if Auto-Trigger mode is used.

The falling edge of FS/CS should not be placed at the precise moment at the end of a conversion (by default

when EOC goes high). Otherwise, the data could be corrupt. If FS/CS is placed before the end of a conversion,

the previous conversion result is read. If FS/CS is placed after the end of a conversion, the current conversion

result is read.

The conversion result is 16-bit data in straight binary format as shown in Table 6. Generally 16 SCLKs are

necessary, but there are exceptions when more than 16 SCLKs are required (see Table 7). Data output from the

serial output (SDO) is left-adjusted MSB first. The trailing bits are filled with three TAG bits first (if enabled) plus

all '0's. SDO remains low until FS/CS is brought high again.

SDO is active when FS/CS is low. The rising edge of FS/CS 3-states the SDO output.

NOTE

Whenever SDO is not in 3-state (that is, when FS/CS is low and SCLK is running), a

portion of the conversion result is output at the SDO pin. The number of bits depends

on how many SCLKs are supplied. For example, a manual channel select command

cycle requires 4 SCLKs. Therefore, four MSBs of the conversion result are output at

SDO. The exception is when SDO outputs all '1's during the cycle immediately after

any reset (POR, software reset, or external reset).

If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all

16 bits from SDO during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case, it is

better to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in Auto-Nap mode).

Table 6. Ideal Input Voltages and Output Codes

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT

Full-scale range

STRAIGHT BINARY

Least significant bit (LSB)

BINARY CODE

HEX CODE

Full-scale

1111 1111 1111 1111

FFFF

Midscale

1000 0000 0000 0000

8000

Midscale – 1 LSB

0111 1111 1111 1111

7FFF

Zero

0 V

0000 0000 0000 0000

0000

TAG Mode

The ADS8331/32 includes a TAG feature that can be used to indicate which channel sourced the converted

result. If TAG mode is enabled, three address bits are added after the LSB of the conversion data is read out

from SDO to indicate which channel corresponds to the result. These address bits are '000' for channel 0, '001'

for channel 1, '010' for channel 2, '011' for channel 3, '100' for channel 4, '101' for channel 5, '110' for channel 6,

and '111' for channel 7. The converter requires at least 19 SCLKs when TAG mode is enabled in order to

transfer the 16-bit conversion result and the three TAG bits.

Daisy-Chain Mode

The ADS8331/32 can operate as a single converter or in a system with multiple converters. System designers

can take advantage of the simple, high-speed, SPI-compatible serial interface by cascading converters in a

single chain when multiple converters are used. The CFR_D5 bit in the Configuration register is used to

reconfigure the EOC/INT status pin as the chain data input (CDI) pin, a secondary serial data input, for the

conversion result from an upstream converter. This configuration is called daisy-chain mode operation. A typical

connection of three converters in daisy-chain mode is shown in Figure 46.

Copyright © 2009, Texas Instruments Incorporated

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