EP1M350 datasheet(7/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–7

Functional Description

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

The enhanced configuration device features multiple configuration schemes. In

addition to supporting the traditional passive serial (PS) configuration scheme for a

single device or a serial device chain, the enhanced configuration device features

concurrent configuration and parallel configuration. With the concurrent

configuration scheme, up to eight PS device chains can be configured simultaneously.

In the FPP configuration scheme, 8-bits of data are clocked into the FPGA each cycle.

These schemes offer significantly reduced configuration times over traditional

schemes.

Furthermore, the enhanced configuration device features a dynamic configuration or

page mode feature. This feature allows you to dynamically reconfigure all the FPGAs

in your system with new images stored in the configuration memory. Up to eight

different system configurations or pages can be stored in memory and selected using

the PGM[2..0] pins. Your system can be dynamically reconfigured by selecting one

of the eight pages and initiating a reconfiguration cycle.

This page mode feature combined with the external flash interface allows remote and

local updates of system configuration data. The enhanced configuration devices are

compatible with the Stratix Remote System Configuration feature.

1 For more information about Stratix Remote System Configuration, refer to the Remote

System Configuration with Stratix & Stratix GX Devices chapter in the Stratix Device

Handbook.

Other user programmable features include:

■

Real-time decompression of configuration data

■

Programmable configuration clock (DCLK)

■

Flash ISP

■

Programmable power-on-reset delay (PORSEL)

FPGA Configuration

FPGA configuration is managed by the configuration controller chip. This process

includes reading configuration data from the flash memory, decompressing it if

necessary, transmitting configuration data via the appropriate DATA[] pins, and

handling error conditions.

After POR, the controller determines the user-defined configuration options by

reading its option bits from the flash memory. These options include the configuration

scheme, configuration clock speed, decompression, and configuration page settings.

The option bits are stored at flash address location 0x8000 (word address) and occupy

512-bits or 32-words of memory. These options bits are read using the internal flash

interface and the default 10 MHz internal oscillator.

After obtaining the configuration settings, the configuration controller chip checks if

the FPGA is ready to accept configuration data by monitoring the nSTATUS and

CONF

_DONE lines. When the FPGA is ready (nSTATUS is high and CONF_DONE is low),

the controller begins data transfer using the DCLK and DATA[] output pins. The

controller selects the configuration page to be transmitted to the FPGA by sampling

its PGM[2..0] pins after POR or reset.

EP1M350 Datasheet(PDF) 7 Page - Altera Corporation

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