Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–15

Functional Description

© December 2009

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Figure 1–4 shows an FPP configuration schematic with the external flash interface in

use.

Intel-Flash-Based EPC Device Protection

In the absence of the lock bit protection feature in the EPC4, EPC8, and EPC16 devices

with Intel flash, Altera recommends four methods to protect the Intel Flash content in

EPC4, EPC8, and EPC16 devices. Any method alone is sufficient to protect the flash.

The methods are listed here in the order of descending protection level:

1. Using an RP# of less than 0.3 V on power-up and power-down for a minimum of

100 ns to a maximum 25 ms disables all control pins, making it impossible for a

write to occur.

Figure 1–4. FPP Configuration with External Flash Interface (Note 1)

Notes to Figure 1–4:

(1) For external flash interface support in EPC8 enhanced configuration device, contact Altera Applications.

(2) Pin A20 in EPC16 devices, pins A20 and A19 in EPC8 devices, and pins A20, A19, and A18 in EPC4 devices should be left floating. These pins

should not be connected to any signal; they are no-connect pins.

(3) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to

F-A16

C-RP#

(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 1–10.

(5) RY/BY# pin is only available for Sharp flash-based EPC8 and EPC16.

Device Protection” on page 1–15.

MSEL

DCLK

DATA[7..0]

nSTATUS

CONF_DONE

nCONFIG

GND

nCE

Stratix Series

or

APEX II Device

WE#

RP#

A[20..0]

RY/BY#

CE#

OE#

DQ[15..0]

PLD or Processor

Enhanced Configuration

Device

DCLK

DATA[7..0]

OE

nCS

nINIT_CONF

WE#C

RP#C

WE#F

RP#F

A[20..0] (2)

RY/BY# (5)

CE#

OE#

DQ[15..0]

GND

EXCLK

WP#

PORSEL

PGM[2..0]

TMO

VCCW

BYTE# (3)

TM1

C-A0 (3)

C-A1 (3)

C-A15 (3)

C-A16 (3)

A0-F

A1-F

A15-F

A16-F

n

nCEO

N.C.

(4)

(4)

(4)

(4)

(4)