t

=

REF

1

f

REF

Time(s)

2.27V

2.64V

t

pul

t

puh

t

rsu

t

delay

t

VCO_CAL

t

PLL_LOCK

Powerup

Reference

Startup

Delay

VCOCalibration

PLLLock

CDCM61002

SCAS870D – FEBRUARY 2009 – REVISED JULY 2010

www.ti.com

APPLICATION INFORMATION

Start-up Time Estimation

The CDCM61002 startup time can be estimated based on the parameters defined in Table 10 and graphically

shown in Figure 17.

Table 10. Start-up Time Dependencies

FORMULA/METHOD OF

PARAMETER

DEFINITION

DESCRIPTION

DETERMINATION

The reciprocal of the applied reference

Reference clock period

frequency in seconds.

Power-supply rise time to low limit of Power

Time required for power

Power-up time (low limit)

On Reset (POR) trip point

supply to ramp to 2.27 V

Power supply rise time to high limit of POR

Time required for power

Power-up time (high limit)

trip point

supply to ramp to 2.64 V

After POR releases, the Colpits oscillator is

enabled. This start-up time is required for the

500 ms best-case and 800 ms

Reference start-up time

oscillator to generate the requisite signal

worst-case

levels for the delay block to be clocked by

the reference input.

Internal delay time generated from the

Delay time

reference clock. This delay provides time for

the reference oscillator to stabilize.

VCO Calibration Time generated from the

reference clock. This process selects the

VCO calibration time

operating point for the VCO based on the

PLL settings.

Based on the 400-kHz loop

Time required for PLL to lock within ±10 ppm

PLL lock time

bandwidth, the PLL settles in

5t or 12.5 ms.

Figure 17. Start-up Time Dependencies

22

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