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TMS320DM6441 Datasheet(PDF) 73 Page - Texas Instruments |
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TMS320DM6441 Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 232 page  4.5.5 PINMUX1 Register Description 4.5.6 Pin Multiplexing Register Field Details 4.5.6.1 EMAC and GPIO3V Pin Multiplexing TMS320DM6441 Digital Media System-on-Chip www.ti.com SPRS359D – SEPTEMBER 2006 – REVISED MARCH 2008 Table 4-14. PINMUX0 Register Field Descriptions (continued) Bit Field Value Description 4 - 0 AEAW EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This enables EMIF address function on default GPIO[10:28] pins. The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in Figure 4-8 and bit field descriptions are given in Table 4-15. More details on the PINMUX1 pin muxing fields are given in Section 4.5.6. A value of "1" enables the secondary or tertiary pin function. Figure 4-8. PINMUX1 Register(1) 31 19 18 17 16 RESERVED TIMIN CLK1 CLK0 R-0000 0000 0000 0 R/W-0 R/W-0 R/W-0 15 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED ASP MSKT SPI I2C PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0 R-0000 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset (1) For proper DM6441 device operation, always write a value of '0' to RSV bit 9. Table 4-15. PINMUX1 Register Field Descriptions Bit Field Value Description 31 - 19 RESERVED Reserved 18 TIMIN Enable TIM_IN function on default GPIO[49] pin 17 CLK1 Enable CLK_OUT1 function on default GPIO[49] pin 16 CLK0 Enable CLK_OUT0 function on default GPIO[48] pin 15 - 11 RESERVED Reserved 10 ASP Enable ASP function on default GPIO[29:34] pins 9 MSKT Enable Memory Stick/Memory Stick PRO function on default MMC/SD/SDIO pins 8 SPI Enable SPI function on default GPIO[37,39:42] pins 7 I2C Enable I2C function on default GPIO[43:44] pins 6 PWM2 Enable PWM2 function on default GPIO[47] pin 5 PWM1 Enable PWM1 function on default GPIO[46] pin 4 PWM0 Enable PWM0 function on default GPIO[45] pin 3 U2FLO Enable UART2 flow control function on default VPFE CI[5:4]/CCD_DATA[13:12] pins 2 UART2 Enable UART2 function on default VPFE CI[7:6]/CCD_DATA[15:14] pins 1 UART1 Enable UART1 function on shared ATA (CF) DMACK, DMARQ pins 0 UART0 Enable UART0 function on default GPIO[35:36] pins The bit fields for various pin multiplexing options within the PINMUX0 and PINMUX1 registers are described in the following sections. The EMAC pin functions are selected as shown in Table 4-16. The functionality for each of the individual pins affected by the PINMUX0 field settings is given in Table 4-17. Submit Documentation Feedback Device Configurations 73 |
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