MSP430F5529 datasheet(22/115 Pages) TI

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MSP430F551x

MSP430F552x

SLAS590D – OCTOBER 2009 – REVISED APRIL 2010

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JTAG Operation

JTAG Standard Interface

The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving

data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the

JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430

development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further

details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide, literature number SLAU278.

Table 7. JTAG Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

PJ.3/TCK

JTAG clock input

PJ.2/TMS

JTAG state control

PJ.1/TDI/TCLK

JTAG data input/TCLK input

PJ.0/TDO

OUT

JTAG data output

TEST/SBWTCK

Enable JTAG pins

RST/NMI/SBWTDIO

External reset

VCC

Power supply

VSS

Ground supply

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface.

Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire

interface pin requirements are shown in Table 8. For further details on interfacing to development tools and

device programmers, see the MSP430 Hardware Tools User's Guide, literature number SLAU278.

Table 8. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL

DIRECTION

FUNCTION

TEST/SBWTCK

Spy-Bi-Wire clock input

RST/NMI/SBWTDIO

IN, OUT

Spy-Bi-Wire data input/output

VCC

Power supply

VSS

Ground supply

Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the

CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the

flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of

128 bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

•

Segments A to D can be erased individually. Segments A to D are also called information memory.

•

Segment A can be locked separately.

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