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R5F2M110ANDD Datasheet(PDF) 28 Page - Renesas Technology Corp |
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R5F2M110ANDD Datasheet(HTML) 28 Page - Renesas Technology Corp |
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28 / 48 page ![]() R8C/M11A Group, R8C/M12A Group 4. Electrical Characteristics Under development Preliminary document Specifications in this document are tentative and subject to change. R01DS0010EJ0010 Rev.0.10 Page 28 of 45 Aug 25, 2010 Notes: 1. Vcc = 2.7 V to 5.5 V and Topr = -20 °C to 85 °C (N version)/-40 °C to 85 °C (D version), unless otherwise specified. 2. Definition of program/erase endurance The number of program/erase cycles is defined on a per-block basis. If the number of cycles is 10,000, each block can be erased 10,000 times. For example, if 1,024 cycles of 1-byte-write are performed to different addresses in 1 Kbyte of block A, and then the block is erased, the number of cycles is counted as one. Note, however, that the same address must not be programmed more than once before completion of an erase (overwriting prohibited). 3. This indicates the number of times up to which all electrical characteristics can be guaranteed after the last programming/ erase operation. Operation is guaranteed for any number of operations in the range of 1 to the specified minimum (Min). 4. In a system that executes multiple program operations, the actual erase count can be reduced by shifting the write addresses in sequence and programming so that as much of the flash memory as possible is used before performing an erase operation. For example, when programming in 16-byte units, the effective number of rewrites can be minimized by programming up to 128 units before erasing them all in one operation. It is also advisable to retain data on the number of erase operations for each block and establish a limit for the number of erase operations performed. 5. If an error occurs during a block erase, execute a clear status register command and then a block erase command at least three times until the erase error does not occur. 6. For information on the program/erase failure rate, contact a Renesas technical support representative. 7. The data hold time includes the time that the power supply is off and the time the clock is not supplied. Figure 4.2 Transition Time until Suspend Table 4.6 Flash Memory (Blocks A and B of Data Flash) Electrical Characteristics Symbol Parameter Condition Standard Unit Min. Typ. Max. — Program/erase endurance (2) 10,000 (3) —— times — Byte programming time — 150 — µs — Block erase time — 0.05 1 s td(SR-SUS) Time delay from suspend request until suspend — — 0.25 + CPU clock × 3 cycles ms — Time from suspend until erase restart — — 30 + CPU clock × 1 cycle µs td(CMDRST- READY) Time from when command is forcibly stopped until reading is enabled — — 30 + CPU clock × 1 cycle µs — Program/erase voltage 1.8 — 5.5 V — Read voltage 1.8 — 5.5 V — Program/erase temperature -20 (N version) —85 °C -40 (D version) —85 °C — Data hold time (7) Ambient temperature = 85 °C 10 — — years Suspend request (FMR21) FST6, FST7: Bits in FST register FMR21: Bit in FMR2 register Fixed time FST6 Clock-dependent time td(SR-SUS) Access restart FST7 |
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