SST26WF032 datasheet(4/36 Pages) SST

4 / 36 page

S71409-01-000

01/10

1.8V Serial Quad I/O (SQI) Flash Memory

SST26WF032

Advance Information

Pin Description

Figure 2: Pin Description for 8-lead SOIC and 8-contact WSON

Table 1: Pin Description

Symbol

Pin Name

Functions

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the

clock input, while output data is shifted out on the falling edge of the clock

input.

SIO[3:0]

Serial Data

Input/Output

To transfer commands, addresses, or data serially into the device or data out

of the device. Inputs are latched on the rising edge of the serial clock. Data is

shifted out on the falling edge of the serial clock. The EQIO command

instruction configures these pins for Quad I/O mode.

Serial Data Input

for SPI mode

To transfer commands, addresses or data serially into the device. Inputs are

latched on the rising edge of the serial clock. SI is the default state after a

power on reset.

Serial Data Output

for SPI mode

To transfer data serially out of the device. Data is shifted out on the falling

edge of the serial clock. SO is the default state after a power on reset.

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain

low for the duration of any command sequence; or in the case of Write oper-

ations, for the command/data input sequence.

VDD

Power Supply

To provide power supply voltage: 1.65-1.95V

VSS

Ground

T1.0 1409

CE#

SO/SIO1

SIO2

VSS

VDD

SIO3

SCK

SI/SIO0

Top View

1409 08-soic S2A P1.0

CE#

SO/SIO1

SIO2

VSS

Top View

VDD

SIO3

SCK

SI/SIO0

1409 08-wson QA P1.0

8-Lead SOIC

8-Contact WSON

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