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PIC18LF4331-E/SP Datasheet(PDF) 184 Page - Microchip Technology |
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PIC18LF4331-E/SP Datasheet(HTML) 184 Page - Microchip Technology |
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184 / 392 page ![]() PIC18F2331/2431/4331/4431 DS39616D-page 184 2010 Microchip Technology Inc. 18.4.4 INTERRUPTS IN DOUBLE UPDATE MODE This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 18-8 shows the interrupts in Continuous Up/Down Count mode with double updates. The Double Update mode provides two additional functions to the user in Center-Aligned mode. 1. The control loop bandwidth is doubled because the PWM duty cycles can be updated twice per period. 2. Asymmetrical center-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. FIGURE 18-8: PWM TIME BASE INTERRUPT, CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES Note: Do not change the PTMOD bits while PTEN is active; it will yield unexpected results. To change the PWM Timer mode of operation, first clear the PTEN bit, load the PTMOD bits with the required data and then set PTEN. Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 1 1 OSC1 PTMR 3FDh 3FEh 3FFh 3FEh 3FDh 1 Case 1: PTMR Counting Upwards Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 Q2 Q1 Q3 Q4 1 1 OSC1 PTMR 002h 001h 000h 001h 002h 1 Case 2: PTMR Counting Downwards 2 Note 1: Interrupt flag bit, PTIF, is sampled here (every Q1). 2: PWM Time Base Period register, PTPER, is loaded with the value, 3FFh, for this example. 1 1 PTIF bit PTMR_INT_REQ PTIF bit PTMR_INT_REQ A: PRESCALER = 1:1 PTDIR bit PTDIR bit |
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