Low-Jitter, Low-Noise LVPECL-to-LVDS Level

Translator in an SC70 Package

_______________________________________________________________________________________

7

Figure 2. DC Load Test Circuit

1.25V

IN+

IN-

1.20V

1.25V

1.20V

OUT-

OUT+

Figure 3. Transition Time and Propagation Delay Test Circuit

PULSE

GENERATOR

IN+

IN-

50

Ω

50

Ω

OUT-

OUT+

Test Circuits and Timing Diagrams

Figure 1. LVPECL Input Bias

OUT-

OUT+

IN+

IN-

Figure 4. Transition Time and Propagation Delay Timing Diagram

IN-

IN+

OUT-

OUT+

OV (DIFFERENTIAL)

OV (DIFFERENTIAL)

OV (DIFFERENTIAL)

80%

80%

20%

20%

OV (DIFFERENTIAL)

OV (DIFFERENTIAL)

OV (DIFFERENTIAL)