Applications Information

Supply Bypassing

ceramic 0.01µF capacitor as close to the device as

possible.

Differential Traces

Input and output trace characteristics affect the perfor-

mance of the MAX9181. Use controlled-impedance dif-

ferential traces. Ensure that noise couples as common

mode by running the traces within a differential pair

close together.

Maintain the distance within a differential pair to avoid

discontinuities in differential impedance. Avoid 90°

turns and minimize the number of vias to further prevent

impedance discontinuities.

Cables and Connectors

The LVDS standards define signal levels for intercon-

nect with a differential characteristic impedance and

termination of 100Ω. Interconnects with a characteristic

impedance and termination of 90Ω to 132Ω impedance

are allowed, but produce different signal levels (see

Termination).

LVPECL signals are typically specified for 50Ω single-

ended characteristic impedance interconnect terminat-

Use cables and connectors that have matched differen-

tial impedance to minimize impedance discontinuities.

Termination

For point-to-point LVDS links, the termination resistor

should be located at the LVDS receiver input and

match the differential characteristic impedance of the

transmission line.

Each line of a differential LVPECL link should be termi-

Thevinin equivalent.

The LVDS output voltage level depends upon the differ-

ential characteristic impedance of the interconnect and

the value of the termination resistance. The MAX9181 is

guaranteed to produce LVDS output levels into 100Ω.

With the typical 3.6mA output current, the MAX9181 pro-

duces an output voltage of 360mV when driving a 100Ω

transmission line terminated with a 100Ω termination

els with different loads, see the Differential Output

Voltage vs. Load Resistor curve in the Typical Operating

Characterics.

Chip Information

TRANSISTOR COUNT: 401

PROCESS: CMOS

Low-Jitter, Low-Noise LVPECL-to-LVDS Level

Translator in an SC70 Package

6

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