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PCA85232DA Datasheet(PDF) 36 Page - NXP Semiconductors |
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PCA85232DA Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 54 page  PCA85232 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 1 — 8 December 2010 36 of 54 NXP Semiconductors PCA85232 LCD driver for low multiplex rates Fig 24. Driver timing waveforms 001aah848 tPD(drv) tSYNC_NL tPD(SYNC_N) CLK SYNC BP0 to BP3, and S0 to S159 tclk(H) tclk(L) 1 / fCLK 0.7 VDD 0.3 VDD 0.7 VDD 0.3 VDD 0.5 V (VDD = 5 V) 0.5 V Fig 25. I2C-bus timing waveforms when SDA and SDAACK are connected 013aaa110 tf 70 % 30 % SDA tf 70 % 30 % S tr 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 1st clock cycle 70 % 30 % 70 % 30 % tr tVD;ACK cont. cont. SDA SCL tSU;STA tHD;STA Sr tSP tSU;STO tBUF P S tHIGH 9th clock tHD;STA tLOW 70 % 30 % tVD;ACK 9th clock tSU;DAT |
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