PPC8567CVTAQJGA datasheet(69/139 Pages) FREESCALE

69 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 47 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8568E SerDes reference clock

input’s DC requirement.

Figure 47. Single-Ended Connection (Reference Only)

13.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50

Ω to match the

transmission line and reduce reflections which are a source of noise to the system.

The detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol based

on application usage. Refer to the following sections for detailed information:

•

Section 14.2, “AC Requirements for PCI Express SerDes Clocks”

•

Section 15.2, “AC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK”

13.2.4.1

Spread Spectrum Clock

SD_REF_CLK/SD_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%

spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

SD_REF_CLK

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip

MPC8568E

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

PPC8567CVTAQJGA Datasheet(PDF) 69 Page - Freescale Semiconductor, Inc