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PPC8567CVTAQJGA Datasheet(PDF) 86 Page - Freescale Semiconductor, Inc |
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PPC8567CVTAQJGA Datasheet(HTML) 86 Page - Freescale Semiconductor, Inc |
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86 / 139 page  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 86 Freescale Semiconductor Serial RapidIO Figure 54. Single Frequency Sinusoidal Jitter Limits 15.8 Receiver Eye Diagrams For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding Bit Error Rate specification (Table 61, Table 62, Table 63) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver Input Compliance Mask shown in Figure 55 with the parameters specified in Table . The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ω +/– 5% differential resistive load. 8.5 UI p-p 0.10 UI p-p Sinusoidal Jitter Amplitude 22.1 kHz 1.875 MHz 20 MHz Frequency |
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