MPC8533E datasheet(23/112 Pages) FREESCALE

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MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

7.2

DUART AC Electrical Specifications

Table 20 provides the AC timing parameters for the DUART interface.

Enhanced Three-Speed Ethernet (eTSEC),

MII Management

This section provides the AC and DC electrical characteristics for enhanced three-speed and MII

management.

8.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII/FIFO

Electrical Characteristics

The electrical characteristics specified here apply to all gigabit media independent interface (GMII), 8-bit

FIFO interface (FIFO), serial media independent interface (MII), ten-bit interface (TBI), reduced gigabit

media independent interface (RGMII), reduced ten-bit interface (RTBI), and reduced media independent

interface (RMII) signals except management data input/output (MDIO) and management data clock

(MDC). The 8-bit FIFO interface can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces are defined

for 2.5 V, while the MII, GMII, TBI, and RMII interfaces can be operated at 3.3 or 2.5 V. Whether the

GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with IEEE 802.3. The

RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII)

Specification Version 1.3 (12/10/2000). The RMII interface follows the RMII Consortium RMII

Specification Version 1.2 (3/20/1998). The electrical characteristics for MDIO and MDC are specified in

Section 9, “Ethernet Management Interface Electrical Characteristics.”

Low-level output voltage (OVDD = min, IOL = 2 mA)

VOL

—0.4

—

Note:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.

Table 20. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

CCB clock/1,048,576

baud

Maximum baud rate

CCB clock/16

baud

Oversample rate

—

Notes:

1. CCB clock refers to the platform clock.

2. Actual attainable baud rate will be limited by the latency of interrupt processing.

3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values

are sampled each sixteenth sample.

Table 19. DUART DC Electrical Characteristics (continued)

Parameter

Symbol

Min

Max

Unit

Notes

MPC8533E Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc

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