MPC8533E datasheet(25/112 Pages) FREESCALE

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MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.3

FIFO, GMII,MII, TBI, RGMII, RMII, and RTBI AC Timing

Specifications

The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI are presented in this

section.

8.3.1

FIFO AC Specifications

The basis for the AC specifications for the eTSEC FIFO modes is the double data rate RGMII and RTBI

specifications, since they have similar performance and are described in a source-synchronous fashion like

FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and

source clock in GMII fashion.

When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the

relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn TSECn_TX_CLK,

while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit

clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out

onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is

intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a

source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since

the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver.

A summary of the FIFO AC specifications appears in Table 23 and Table 24.

Table 23. FIFO Mode Transmit AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

TX_CLK, GTX_CLK clock period

tFIT

—8.0

—

TX_CLK, GTX_CLK duty cycle

tFITH

—

TX_CLK, GTX_CLK peak-to-peak jitter

tFITJ

——

250

Rise time TX_CLK (20%–80%)

tFITR

—

0.75

—

Fall time TX_CLK (80%–20%)

tFITF

—

0.75

—

GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN

hold time

tFITDX

0.5

—

3.0

Note:

1. Data valid tFITDV to GTX_CLK Min setup time is a function of clock period and max hold time.

(Min setup = Cycle time – Max hold).

Table 24. FIFO Mode Receive AC Timing Specification

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

RX_CLK clock period

tFIR

—8.0

—

RX_CLK duty cycle

tFIRH/tFIRH

—

RX_CLK peak-to-peak jitter

tFIRJ

——

250

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