AT91SAM7L64 datasheet(21/564 Pages) ATMEL

21 / 564 page

6257A–ATARM–20-Feb-08

AT91SAM7L128/64 Preliminary

Processor and Architecture

7.1

ARM7TDMI Processor

• RISC processor based on ARMv4T Von Neumann Architecture

– Runs at up to 36 MHz, providing 0.9 MIPS/MHz

• Two instruction sets

–ARM

® high-performance 32-bit instruction set

– Thumb high code density 16-bit instruction set

• Three-stage pipeline architecture

– Instruction Fetch (F)

– Instruction Decode (D)

– Execute (E)

7.2

Debug and Test Features

• Integrated embedded in-circuit emulator

– Two watchpoint units

– Test access port accessible through a JTAG protocol

– Debug communication channel

• Debug Unit

–Two-pin UART

– Debug communication channel interrupt handling

– Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

7.3

Memory Controller

• Programmable Bus Arbiter

– Handles requests from the ARM7TDMI and the Peripheral DMA Controller

• Address decoder provides selection signals for

– Five internal 1 Mbyte memory areas

– One 256 Mbyte embedded peripheral area

• Abort Status Registers

– Source, Type and all parameters of the access leading to an abort are saved

– Facilitates debug by detection of bad pointers

• Misalignment Detector

– Alignment checking of all data accesses

– Abort generation in case of misalignment

• Remap Command

– Remaps the SRAM in place of the embedded non-volatile memory

– Allows handling of dynamic exception vectors

– Peripheral protection against write and/or user access

• Enhanced Embedded Flash Controller

AT91SAM7L64 Datasheet(PDF) 21 Page - ATMEL Corporation

AT91SAM7L64 Datasheet(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL