HT66F13 datasheet(104/173 Pages) HOLTEK

104 / 173 page

Single Pulse Output Mode

To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10

respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to

11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse

on the TM output pin.

The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which

can be implemented using the application program. The trigger for the pulse TPnB output leading edge

is a compare match from Comparator B, which can be implemented using the application program.

However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low

to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When

the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of

TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The

generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to

zero, which can be implemented using the application program or when a compare match occurs from

Comparator A.

HT66F13/HT66F14/HT66F15

Enhanced A/D Flash Type MCU

Rev. 1.10

104

February 9, 2011

Counter Value

CCRA

TnON

TnPAU

TnBPOL

CCRA Int.

Flag TnAF

CCRB Int.

Flag TnBF

Time

Pause

Resume

Stop

Counter

Restart

TnCCLR = 1; TnBM [1:0] = 10;

TnPWM [1:0] = 11

Output Pin

Reset to Initial value

Output controlled

by other pin-shared

function

CCRB

TPnB Pin

(TnBOC=1)

TPnB Pin

(TnBOC=0)

Duty Cycle set by CCRB

PWM Period set by CCRA

Output Inverts

when TnBPOL is high

CCRP Int.

Flag TnPF

ETM PWM Mode -- Centre Aligned

Note:

1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period

2. TnPWM [1:0] =11 therefore the PWM is centre aligned

3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01

4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty

5. CCRP will generate an interrupt request when the counter decrements to its zero value

HT66F13 Datasheet(PDF) 104 Page - Holtek Semiconductor Inc

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