HT82K70E-L datasheet(30/59 Pages) HOLTEK

30 / 59 page

HT82K70E-L/HT82K70A-L/HT82K76E-L

Rev. 1.20

February 1, 2011

6 - b i t C o u n t e r

(

¸ 6 4 )

7 - b i t P r e s c a l e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

W D T C l o c k S o u r c e

C l e a r W D T T y p e

C o n f i g u r a t i o n O p t i o n

C L R W D T 1 F l a g

C L R W D T 2 F l a g

1 o r 2 I n s t r u c t i o n s

C L R

f S Y S / 4

W D T O s c i l l a t o r

W D T C l o c k S o u r c e

C o n f i g u r a t i o n O p t i o n

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise. It operates by providing a de-

vice reset when the WDT counter overflows. The WDT

clock is supplied by its own internal dedicated internal

WDT oscillator or by the fSYS/4 clock source. Note that if

the WDT enable/disable configuration option has been

disabled, then any instruction relating to its operation

will result in no operation.

The WDT enable/disable is controlled using a bit in the

CTLR register. The WDT clock source and clear instruc-

tion type are selected through configuration options.

However, it should be noted that the WDT oscillator

clock period can vary with VDD, temperature and pro-

cess variations. Whether the WDT clock source is its

own internal WDT oscillator, it is further divided by an in-

ternal 6-bit counter and a clearable single bit counter to

give longer Watchdog time-outs. As the clear instruction

only resets the last stage of the divider chain, for this

reason the actual division ratio and corresponding

Watchdog Timer time-out can vary by a factor of two.

The exact division ratio depends upon the residual value

in the Watchdog Timer counter before the clear instruc-

tion is executed. It is important to realise that as there

are no independent internal registers or configuration

options associated with the length of the Watchdog

Timer time-out, it is completely dependent upon the fre-

quency the internal WDT oscillator.

Under normal program operation, a WDT time-out will

initialise a device reset and set the status bit TO. How-

ever, if the system is in the Power Down Mode, when a

WDT time-out occurs, the TO bit in the status register

will be set and only the Program Counter and Stack

Pointer will be reset. Three methods can be adopted to

clear the contents of the WDT. The first is an external

hardware reset, which means a low level on the RES

pin, the second is using the watchdog software instruc-

tions and the third is via a HALT instruction.

There are two methods of using software instructions to

clear the Watchdog Timer, one of which must be chosen

by configuration option. The first option is to use the sin-

gle

²CLR WDT² instruction while the second is to use

the two commands

²CLR WDT1² and ²CLR WDT2². For

the first option, a simple execution of

²CLR WDT² will

clear the WDT while for the second option, both

²CLR

WDT1

² and ²CLR WDT2² must both be executed to

successfully clear the WDT. Note that for this second

option, if

²CLR WDT1² is used to clear the WDT, succes-

sive executions of this instruction will have no effect,

only the execution of a

²CLR WDT2² instruction will

clear the WDT. Similarly after the

²CLR WDT2² instruc-

tion has been executed, only a successive

²CLR WDT1²

instruction can clear the Watchdog Timer.

W S 2

W D T S R e g i s t e r

b 7

b 0

W D T p r e s c a l e r r a t e s e l e c t

W S 2

W S 1

W S 0

W D T R a t e

D i s a b l e W D T

1 : 1

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

N o t u s e d

W S 1 W S 0

Watchdog Timer Register for HT82K76E-L

HT82K70E-L Datasheet(PDF) 30 Page - Holtek Semiconductor Inc

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