HT82K70E-L datasheet(33/59 Pages) HOLTEK

33 / 59 page

HT82K70E-L/HT82K70A-L/HT82K76E-L

Rev. 1.20

February 1, 2011

SPI Serial Interface

The device include single SPI Serial Interfaces. The SPI

interface is a full duplex serial data link, originally de-

signed by Motorola, which allows multiple devices con-

nected to the same SPI bus to communicate with each

other. The devices communicate using a master/slave

technique where only the single master device can initi-

ate a data transfer. A simple four line signal bus is used

for all communication.

SPI Interface Communication

Four lines are used for SPI communication known as

SDI - Serial Data Input, SDO - Serial Data Output, SCK -

Serial Clock and SCS - Slave Select. Note that the con-

dition of the Slave Select line is conditioned by the

CSEN bit in the SBCR control register. If the CSEN bit is

high then the SCS line is active while if the bit is low then

the SCS line will be in a floating condition. The following

timing diagram depicts the basic timing protocol of the

SPI bus.

SPI Registers

There are three registers associated with the SPI Inter-

face. These are the SBCR register which is the control

WSR low nibble byte which is the SPI mode control reg-

ister. The SBCR register is used to setup the required

setup parameters for the SPI bus and also used to store

associated operating flags, while the SBDR register is

used for data storage.

The WSR register low nibble byte is used to select SPI

mode, clock polarity edge selection and SPI enable or

disable selection.

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

S B D R ( R e c e i v e d D a t a R e g i s t e r )

S D O B u f f e r

M L S

D a t a B u s

M a s t e r o r S l a v e

S D I

S D O

I n t e r n a l B a u d R a t e C l o c k

S C K

C l o c k P o l a r i t y

C 2

C 1

C 0

S B E N

I n t e r n a l B u s y F l a g

S B E N

W r i t e S B D R

W C O L F l a g

T R F

a n d , s t a r t

S B E N

E N

A N D

W r i t e S B D R

W r i t e S B D R E n a b l e / D i s a b l e

S C S

E N

M a s t e r o r S l a v e

C S E N

S B E N

a n d , s t a r t

SPI Block Diagram

Note:

WCOL: set by SPI cleared by users

CSEN: enable/disable chip selection function pin

master mode: 1/0 = with/without SCS output function

Slave mode: 1/0 = with/without SCS input control function

SBEN: enable/disable serial bus (0: initialise all status flags)

when SBEN=0, all status flags should be initialised

when SBEN=1, all SPI related function pins should stay at floating state

TRF: 1 = data transmitted or received, 0= data is transmitting or still not received

CPOL: I/O = clock polarity rising/falling edge: WSR register bit 0

If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0)

SCK is the serial clock timing.

HT82K70E-L Datasheet(PDF) 33 Page - Holtek Semiconductor Inc

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