HT82K70E-L datasheet(31/59 Pages) HOLTEK

31 / 59 page

HT82K70E-L/HT82K70A-L/HT82K76E-L

Rev. 1.20

February 1, 2011

W S 2

W D T S R e g i s t e r

b 7

b 0

W D T p r e s c a l e r r a t e s e l e c t

W S 2

W S 1

W S 0

W D T R a t e

D i s a b l e W D T

1 : 1

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

P C 0 / P C 1 r e s i s t o r s e l e c t

1 : 4 . 7 k W

0 : 3 0 k W ( d e f a u l t )

( C o n f i g u r a t i o n o p t i o n e n a b l e P C 0 ~ P C 3 p u l l - h i g h

o p t i o n , t h a n t h e b i t s e t t i n g s f o r t h e e f f e c t i v e )

N o t u s e d

W S 1 W S 0

P S 2 R

Watchdog Timer Register for HT82K70E-L and HT82K70A-L

Bit

Name

Description

Z2_WAKEUP

Read only bit.

1: Z2 changed before Z1

0: default

Z1_WAKEUP

Read only bit.

1: Z1 changed before Z2

0: default

V2_WAKEUP

Read only bit.

1: V2 changed before V1

0: default

V1_WAKEUP

Read only bit.

1: V1 changed before V2

0: default

SPI_EN

This bit control the shared PIN (SCS, SDI, SDO and SCK) is SPI or GPIO mode

1: SPI mode

0: IO mode (default)

SPI_CSEN

1: enable, this bit is used to enable/disable software CSEN function

0: disable, SCS define as GPIO (default)

CKEG

1: SPI first output the data immediately after the SPI is enable. And SPI output the data in

the falling edge(polarity=0) or rising edge (polarity=1); SPI read data in the in the rising

edge (polarity=0) or falling edge (polarity=1);

0: SPI output the data in the rising edge(polarity=0) or falling edge (polarity=1);

SPI read data in the in the falling edge(polarity=0) or rising edge (polarity=1); (default)

SPI_ CPOL

1: clock polarity rising

0: clock polarity falling (default)

Note: The Internal Register bit4~bit7 data will clear to zero after F/W read the register.

Wake-up Status Register

- WSR

HT82K70E-L Datasheet(PDF) 31 Page - Holtek Semiconductor Inc

HT82K70E-L Datasheet(HTML) 31 Page - Holtek Semiconductor Inc

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