AD9146BCPZ datasheet(43/52 Pages) AD

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AD9146

Rev. 0 | Page 43 of 52

The Tx enable feature also allows for an extended delay from

when the TXENABLE pin is brought high to when the DAC

outputs begin transmitting the data present in the FIFO and

datapath. Two different delay lengths are available. These delays

allow the part to be set up properly during the delay time with-

out transmitting false data and to begin receiving correct data

after the datapath is flushed. The amount of delay time to be

allotted for various wake-up times depends on the delay setting

used, as well as which portions of the DAC are powered down

and need to be reinitialized.

Table 23 lists the minimum wait time required for the DAC to

begin transmitting again after the TXENABLE pin is brought

high. Regardless of the delay setting, there is an inherent fixed

delay of 10 DAC clock cycles for all the options listed in Table 23

before the DAC begins transmitting. Additionally, because the

Tx enable logic is timed from a divided-down rate of the DAC

clock—specifically, DAC/64—the number of edges that the part

waits for before allowing data to be transmitted from the DAC can

vary. Because the synchronization between the DAC/64 clock and

the Tx enable logic trigger is unknown, the number of DAC/64

clock edges that must be waited for before the outputs are released

can vary by up to one cycle.

Table 23. Wake-Up Time for Various Tx Enable Delay Settings

Number of

DAC/64 Edges

to Wait1

Additional

DAC Edges

to Wait

Minimum

Wait Time2

No extended

delay (0x00)

360.82 ns

Extended

Delay 0 (0x20)

4.18

μs

Extended

Delay 1 (0x60)

6.611

μs

1 Values may vary by up to one DAC/64 cycle for the amount of wake-up time

of each delay setting.

2 Values based on 737.28 MHz DAC rate condition; uses (number of DAC/64 +

10 DAC clocks) for calculation.

For timing purposes and to ensure that incorrect data is flushed,

the minimum wake-up time must be considered. This constraint

determines how soon the datapath must begin to be flushed.

Depending on which portions of the DAC are powered down

using the Tx enable feature, the amount of time required to start

setting up the part and flushing the datapaths must be adjusted.

An appropriate delay setting is required to accommodate the

earliest possible wake-up time needed for flushing before the

outputs are enabled.

In addition to the delays listed in Table 23, specific wake-up

times for individual powered-down portions of the AD9146

must be accounted for during the preparation time.

The following example provides a typical configuration that

uses the Tx enable feature to power down the interpolation

filters. This example provides guidelines for how to determine

the amount of wake-up time to design in a system.

•

fDATA = 184.32 MHz

•

fDAC = 737.28 MHz

•

Interpolation = 4×

•

Inverse sinc on

•

Tx enable filter power-down option selected

•

Datapath flush time = 175 DAC clocks

•

tDAC = 1.36 ns

•

tDPFLUSH = 238 ns

The minimum wake-up time with no delay setting is 360.82 ns

(see Table 23). In this example, the time required to flush the

datapath is only 238 ns. Therefore, if datapath flushing is done

simultaneous to the TXENABLE pin being brought high, there

is enough time for the flush to complete before the minimum

possible time that the outputs can begin transmitting. For each

individual case, the amount of time needed to flush the data-

path must be accounted for when calculating the minimum

time after which the DACs can begin transmitting data.

The TXENABLE pin must be held high while the part is being

powered up. After the part is powered up, the pin can be brought

low to clamp the outputs, when desired. Note that the pin

cannot be held low during power-up because the circuit logic is

transition sensitive and the part must see a falling edge before it

clamps the outputs.

TEMPERATURE SENSOR

The AD9146 has a band gap temperature sensor for monitoring

the temperature change of the AD9146. The temperature must

be calibrated against a known temperature to remove the part-

to-part variation on the band gap circuit used to sense the

temperature. The DACCLK must be running at a minimum

of 100 MHz to obtain a reliable temperature measurement.

To monitor temperature change, the user must take a reading

at a known ambient temperature for a single-point calibration

of each AD9146 device.

Tx = TREF + 7.7 × (Code_x − Code_ref)/1000 + 1

where:

Code_x is the readback code at the unknown temperature, Tx.

Code_ref is the readback code at the calibrated temperature, TREF.

To use the temperature sensor, it must be enabled by setting

ings, the die temperature range control register (Register 0x48)

should be set to 0x02.

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