AD9146BCPZ datasheet(19/52 Pages) AD

19 / 52 page

AD9146

Rev. 0 | Page 19 of 52

Table 11. Device Configuration Register Descriptions

Name

Address

(Hex)

Bits

Name

Description

Default

Comm

0x00

SDIO

SDIO pin operation. To enable data readback, set this bit to 1.

0 = SDIO operates as an input only.

1 = SDIO operates as a bidirectional input/output.

LSB_FIRST

Serial port communication, LSB or MSB first.

0 = MSB first.

1 = LSB first.

Reset

The device is placed in reset when this bit is written high

and remains in reset until the bit is written low.

Power

Control

0x01

Power down I DAC

1 = power down I DAC.

Power down Q DAC

1 = power down Q DAC.

Power down data

receiver

1 = power down the input data receiver.

Power down auxiliary

ADC

1 = power down the auxiliary ADC for temperature sensor.

Power down auxiliary

DACs and reference

1 = power down the auxiliary DACs and the voltage reference.

Power down clocks

1 = power down the clocks.

Tx Enable

Control

0x02

Extended delay length

Time delay from when the TXENABLE pin is brought high to

when the DAC begins transmitting data. See the T

x Enable

section for more information.

0 = delay the outputs by 12 to 13 DAC/64 clock edges.

1 = delay the outputs by 19 to 20 DAC/64 clock edges.

Enable extended delay

The transmit delay, regardless of whether the extended delay

option is selected, has an inherent fixed delay of 10 DAC clock

cycles. When the extended delay is disabled, there is a mini-

mum delay time in the outputs of 1 to 2 DAC/64 clock edges

from when the TXENABLE pin is brought high.

0 = disable the extended delay option. Delays the outputs

by 1 to 2 DAC/64 clock edges.

1 = enable the extended delay option. Delays the outputs

based on the setting of Bit 6.

Power down voltage

reference

0 = no power-down of the internal voltage reference.

1 = power down the internal voltage reference when the

TXENABLE pin is held low.

Power down PLL

0 = no power-down of the on-chip PLL.

1 = power down the on-chip PLL when the TXENABLE pin is

held low.

Power down DACs

0 = no power-down of the DAC cores.

1 = power down the DAC cores when the TXENABLE pin is

held low.

Power down FIFO

0 = no power-down of the FIFO.

1 = power down the FIFO when the TXENABLE pin is held

low.

Power down filters

0 = no power-down of the interpolation filters.

1 = power down the interpolation filters when the

TXENABLE pin is held low.

AD9146BCPZ Datasheet(PDF) 19 Page - Analog Devices

AD9146BCPZ Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL