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AD9146BCPZ Datasheet(PDF) 21 Page - Analog Devices

Part # AD9146BCPZ
Description  Dual, 16-Bit, 1230 MSPS, TxDAC Digital-to-Analog Converter
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9146BCPZ Datasheet(HTML) 21 Page - Analog Devices

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AD9146
Rev. 0 | Page 21 of 52
Register
Name
Address
(Hex)
Bits
Name
Description
Default
Clock
Receiver
Control
0x08
7
DACCLK duty correction
1 = enable duty cycle correction on the DACCLK input.
0
6
REFCLK duty correction
1 = enable duty cycle correction on the REFCLK input.
0
5
DACCLK cross-correction
1 = enable differential crossing correction on the DACCLK
input.
1
4
REFCLK cross-correction
1 = enable differential crossing correction on the
REFCLK input.
1
PLL
Control
0x0A
7
PLL enable
1 = enable the PLL clock multiplier. The REFCLK input is
used as the PLL reference clock signal.
0
6
PLL manual enable
1 = enable manual selection of the VCO band. The correct
VCO band must be determined by the user and written to
Bits[5:0].
1
[5:0]
Manual VCO Band[5:0]
Selects the VCO band to be used.
000000
0x0C
[7:6]
PLL Loop Bandwidth[1:0]
Selects the PLL loop filter bandwidth.
11
00 = widest bandwidth.
…
11 = narrowest bandwidth.
[4:0]
PLL Charge Pump
Current[4:0]
Sets the nominal PLL charge pump current.
10001
00000 = lowest current setting.
…
11111 = highest current setting.
0x0D
[7:6]
N2[1:0]
PLL control clock divider. This divider determines the ratio
of the DACCLK frequency to the PLL controller clock
frequency. fPC_CLK must always be less than 75 MHz.
11
00 = fDACCLK/fPC_CLK = 2.
01 = fDACCLK/fPC_CLK = 4.
10 = fDACCLK/fPC_CLK = 8.
11 = fDACCLK/fPC_CLK = 16.
4
PLL cross-control enable
1 = enable PLL cross-point controller.
1
[3:2]
N0[1:0]
PLL VCO divider. This divider determines the ratio of the
VCO frequency to the DACCLK frequency.
10
00 = fVCO/fDACCLK = 1.
01 = fVCO/fDACCLK = 2.
10 = fVCO/fDACCLK = 4.
11 = fVCO/fDACCLK = 4.
[1:0]
N1[1:0]
PLL loop divider. This divider determines the ratio of the
DACCLK frequency to the REFCLK frequency.
01
00 = fDACCLK/fREFCLK = 2.
01 = fDACCLK/fREFCLK = 4.
10 = fDACCLK/fREFCLK = 8.
11 = fDACCLK/fREFCLK = 16.
PLL Status
0x0E
7
PLL locked
1 = the PLL-generated clock is tracking the REFCLK input
signal.
N/A
[3:0]
VCO Control Voltage[3:0]
VCO control voltage readback. See Table 22.
N/A
0x0F
[5:0]
VCO Band Readback[5:0]
Indicates the VCO band currently selected.
N/A



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