LPC1850 datasheet(59/142 Pages) NXP

59 / 142 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 2.2 — 9 September 2011

59 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

[1]

x = available; - = not pinned out.

[2]

I = input, O = output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDD(IO)); F = floating.

[3]

5 V tolerant pad with 15 ns glitch filter; provides digital I/O functions with TTL levels and hysteresis; normal drive strength.

[4]

5 V tolerant pad with 15 ns glitch filter providing digital I/O functions with TTL levels, and hysteresis; high drive strength.

[5]

5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis.

[6]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC

input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function

and disabling the pull-up resistor through the pin’s SFSP register.

[7]

5 V tolerant transparent analog pad.

[8]

Transparent analog pad. Not 5 V tolerant.

[9]

Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only). This pad is not 5 V tolerant.

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output with weak pull-up resistor and hysteresis.

[12] On the TFBGA100 package, VPP is internally connected to VDDIO.

[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.

[14] On the TFBGA100 and LQFP100 packages, VSS is internally connected to VSSIO.

VSSIO

C4,

D13,

G6,

G7,

G8,

H8,

H9,

J8,

J9,

K9,

K10,

M13,

P7,

P13

40,

76,

109

[13]

[14]

Ground.

VSSA

135

Analog ground.

Not connected

-B9

n.c.

Table 3.

Pin description …continued

LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.

Symbol

Description

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