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STM32F405XX Datasheet(PDF) 23 Page - STMicroelectronics |
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STM32F405XX Datasheet(HTML) 23 Page - STMicroelectronics |
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23 / 154 page  STM32F405xx, STM32F407xx Description Doc ID 022152 Rev 1 23/154 VDD minimum value is 1.8 V (a). There are three low-power modes: – MR is used in the nominal regulation mode (Run) – LPR is used in the Stop modes – Power-down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost). ● Regulator ON/internal reset OFF The regulator ON with internal reset OFF mode is not available on LQFP64 package. On LQFP100 and LQFP144 packages, the internal reset is controlled by setting PDR_ON pin to VSS. On UFBGA176 package, the internal regulator must be activated by connecting BYPASS_REG to VSS, and PDR_ON to VSS. On LQFP176 packages, the internal reset must be activated by connecting PDR_ON to VSS. The NRST pin should be controlled by an external reset controller to keep the device under reset when VDD is below 1.8 V (see Figure 7). Figure 7. Regulator ON/internal reset OFF a. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C temperature range and PDR_ON is connected to VSS. |
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