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TUSB1310A Datasheet(PDF) 2 Page - Texas Instruments |
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TUSB1310A Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 42 page ![]() TUSB1310A SLLSE32D – NOVEMBER 2010 – REVISED MAY 2011 www.ti.com Contents 1 PRODUCT OVERVIEW ......................................................................................................... 7 1.1 Features ...................................................................................................................... 7 1.2 Target Applications ......................................................................................................... 7 1.3 Introduction .................................................................................................................. 8 1.4 Functional Block Diagram .................................................................................................. 8 2 PIN DESCRIPTIONS ........................................................................................................... 10 2.1 Configuration Pins ......................................................................................................... 10 2.2 PIPE ......................................................................................................................... 10 2.3 ULPI ......................................................................................................................... 13 2.3.1 ULPI Modes ..................................................................................................... 13 2.4 Clocking ..................................................................................................................... 14 2.5 JTAG Interface ............................................................................................................. 14 2.6 Reset and Output Control Interface ..................................................................................... 14 2.7 Strap Options .............................................................................................................. 14 2.8 USB Interfaces ............................................................................................................. 15 2.9 Special Connect ........................................................................................................... 15 2.10 Power and Ground ........................................................................................................ 16 3 FUNCTIONAL DESCRIPTION ............................................................................................... 18 3.1 Power On and Reset ...................................................................................................... 18 3.1.1 RESETN and PHY_RESETN – Hardware Reset .......................................................... 18 3.1.2 ULPI Reset – Software Reset ................................................................................. 18 3.1.3 OUT_ENABLE - Output Enable .............................................................................. 18 3.1.4 Power Up Sequence ........................................................................................... 18 3.2 Clocks ....................................................................................................................... 19 3.2.1 Clock Distribution ............................................................................................... 19 3.2.2 Output Clock .................................................................................................... 19 3.3 Power Management ....................................................................................................... 19 3.3.1 USB Power Management ...................................................................................... 20 3.4 Receiver Status ............................................................................................................ 21 3.4.1 Clock Tolerance Compensation .............................................................................. 21 3.4.2 Receiver Detection ............................................................................................. 21 3.4.3 8b/10b Decode Errors .......................................................................................... 22 3.4.4 Elastic Buffer Errors ............................................................................................ 22 3.4.5 Disparity Errors ................................................................................................. 22 3.5 Loopback ................................................................................................................... 22 3.6 Adaptive Equalizer ........................................................................................................ 23 4 REGISTERS ...................................................................................................................... 24 4.1 Register Definitions ........................................................................................................ 24 4.2 Register Map ............................................................................................................... 24 4.2.1 Vendor ID and Product ID (00h-03h) ........................................................................ 24 4.2.2 Function Control (04h-06h) .................................................................................... 25 4.2.3 Interface Control (07h-09h) .................................................................................... 26 4.2.4 OTG Control ..................................................................................................... 26 4.2.5 USB Interrupt Enable Rising (0Dh-0Fh) ..................................................................... 26 4.2.6 USB Interrupt Enable Falling (10h-12h) ..................................................................... 27 2 Contents Copyright © 2010–2011, Texas Instruments Incorporated |
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