Rev. 1.00

17

November 22, 2011

HT16C21

Write Operation

Byte Writes Operation

●

Command Byte

A Command Byte write operation requires a START condition, a slave address with an R/W bit, a command byte,

a command setting byte and a STOP condition for a command byte write operation.

Slave Address

ACK

Write

Command byte

ACK

S

0

1

1

1

0

0

0

0

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

Command setting

ACK

P

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

Command Byte Write Operation

●

Display RAM Single Data Byte

A display RAM data byte write operation requires a START condition, a slave address with an R/W bit, a

command byte, a valid Register Address byte, a Data byte and a STOP condition.

Slave Address

ACK

Write

Command byte

ACK

S 0 1 1 1 0 0 0 0

Data byte

ACK

P

D7 D6 D5 D4 D3 D2 D1 D0

Register Address byte

ACK

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

Display RAM Single Data Byte Write Operation

Display RAM Page Write Operation

command byte and the specified display RAM Register Address of which the contents are written to the internal

address pointer. The data to be written to the memory will be transmitted next and then the internal address pointer

will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock

pulse. After the internal address point reaches the maximum memory address, which is 09H for 1/4 duty drive

mode or 0FH for 1/8 duty drive mode, the address pointer will be reset to 00H.

Slave Address

ACK

Write

ACK

S

0

1

1

1

0

0

0

0

ACK

ACK

Data byte

P

D7

D6

D5

D4

D3

D2

D1

D0

Data byte

D7

D6

D5

D4

D3

D2

D1

D0

ACK

ACK

Data byte

D7

D6

D5

D4

D3

D2

D1

D0

ACK

Register Address byte

Command byte

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

N Bytes Display RAM Data Write Operation