SIC403 datasheet(12/25 Pages) VISHAY

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Document Number: 66550

S11-1638-Rev. B, 15-Aug-11

Vishay Siliconix

SiC403

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Because the on-times are forced to occur at intervals no

greater than 40 µs, the frequency will not fall below ~ 25 kHz.

Figure 5 shows ultra-sonic power-save operation.

Benefits of Ultrasonic Power-Save

Having a fixed minimum frequency in power-save has some

significant advantages as below:

• The minimum frequency of 25 kHz is outside the audible

range of human ear. This makes the operation of the

SiC403 very quiet.

• The output voltage ripple seen in power-save mode is

significant lower than conventional power-save, which

improves efficiency at light loads.

• Lower ripple in power-save also makes the power

component selection easier.

Figure 6 shows the behavior under power-save and

continuous conduction mode at light loads.

Smart Power-Save Protection

Active loads may leak current from a higher voltage into the

switcher

output.

Under

light

load

conditions

with

power-save-power-save enabled, this can force VOUT to

slowly rise and reach the over-voltage threshold, resulting in

a hard shutdown. Smart power-save prevents this condition.

When the FB voltage exceeds 10 % above nominal (exceeds

825 mV), the device immediately disables power-save, and

DL drives high to turn on the low-side MOSFET. This draws

current from VOUT through the inductor and causes VOUT to

fall. When VFB drops back to the 750 mV trip point, a normal

tON switching cycle begins.

This method prevents a hard OVP shutdown and also cycles

energy from VOUT back to VIN. It also minimizes operating

power by avoiding forced conduction mode operation.

Figure 7 shows typical waveforms for the smart power-save

feature.

Current Limit Protection

The SiC403 features programmable current limit capability,

which is accomplished by using the RDS(ON) of the lower

MOSFET for current sensing. The current limit is set by RILIM

resistor. The RILIM resistor connects from the ILIM pin to the

LX pin which is also the drain of the low-side MOSFET.

When the low-side MOSFET is on, an internal ~ 10 µA

current flows from the ILIM pin and the RILIM resistor, creating

a voltage drop across the resistor. While the low-side

MOSFET is on, the inductor current flows through it and

creates a voltage across the RDS(ON). The voltage across the

MOSFET is negative with respect to ground.

If this MOSFET voltage drop exceeds the voltage across

RILIM, the voltage at the ILIM pin will be negative and current

limit will activate. The current limit then keeps the low-side

MOSFET on and will not allow another high-side on-time,

until the current in the low-side MOSFET reduces enough to

bring the ILIM voltage back up to zero. This method regulates

the inductor valley current at the level shown by ILIM in

figure 8.

Setting the valley current limit to 6 A results in a 6 A peak

inductor current plus peak ripple current. In this situation, the

average (load) current through the inductor is 6 A plus

one-half the peak-to-peak ripple current.

The

internal

µA

current

source

temperature

compensated at 4100 ppm in order to provide tracking with

the RDS(ON). The RILIM value is calculated by the following

equation.

RILIM = 1176 x ILIM

Figure 6 - Ultrasonic Power-Save Operation Mode

Figure 7 - Smart Power-Save

Figure 8 - Valley Current Limit

VOUT drifts up to due to leakage

current flowing into COUT

Smart power save

threshold (825 mV)

threshold

DH and DL off

High-side

drive (DH)

Low-side

drive (DL)

Normal VOUT ripple

VOUT discharges via inductor

and low-side MOSFET

Single DH on-time pulse

after DL turn-off

Normal DL pulse after DH

on-time pulse

DL turns on when smart

PSAVE threshold is reached

DL turns off FB

threshold is reached

IPEAK

ILOAD

ILIM

Time

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