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HT46R92 Datasheet(PDF) 16 Page - Holtek Semiconductor Inc |
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HT46R92 Datasheet(HTML) 16 Page - Holtek Semiconductor Inc |
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16 / 61 page ![]() HT46R92 Rev. 1.10 16 November 5, 2008 Programming Considerations Within the user program, one of the first things to con- sider is port initialisation. After a reset, all of the I/O data (except PC) and port control registers will be set high. This means that all of the PC, PD and PE output pins will be in a output floating condition. Also all the PA and PB I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC and PBC, are then programmed to setup some pins as outputs, these output pins will have an ini- tial high output value unless the associated port data registers, PA and PB, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the ²SET [m].i ² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write opera- tion takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. V D D P A 0 / B Z P A 1 / B Z P A 2 / T M R P A 3 P A 4 / P W M 0 P A 5 / P W M 1 P A 6 P A 7 M U X W a k e - u p O p t i o n S y s t e m W a k e - u p ( P A o n l y ) R e a d D a t a R e g i s t e r D Q C K S D Q C K Q S C o n t r o l B i t P u l l - H i g h O p t i o n D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e D a t a R e g i s t e r D a t a B i t Q M U X P W M o r B Z / B Z P W M o r B Z / B Z O p t i o n T M R f o r P A 2 o n l y PA Input/Output Ports V D D M U X R e a d D a t a R e g i s t e r C o n t r o l B i t D a t a B u s W r i t e C o n t r o l R e g i s t e r C h i p R e s e t R e a d C o n t r o l R e g i s t e r W r i t e D a t a R e g i s t e r D a t a B i t P B 0 / A N 0 P B 1 / A N 1 P B 2 / A N 2 P B 3 / A N 3 P B 4 / A N 4 P B 5 / A N 5 P B 6 P B 7 D Q C K S Q D Q C K S Q L C D E N A C S 2 ~ A C S 0 T o A / D C o n v e r t e r A n a l o g I n p u t S e l e c t o r P C R 2 P C R 1 P C R 0 PB Input/Output Ports |
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