HT46R92 datasheet(20/61 Pages) HOLTEK

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HT46R92

Rev. 1.10

November 5, 2008

The prescaler bit settings have no effect if an external

clock source is used. If the timer is in the Event Count or

Pulse Width Measurement mode, the active transition

edge level type is selected by the logic level of bit 3 of

the Timer Control Register which is known as TE.

Configuring the Timer Mode

In this mode, the Timer/Event Counter can be utilised to

measure fixed time intervals, providing an internal inter-

rupt signal each time the counter overflows. To operate

in this mode, the Operating Mode Select bit pair in the

appropriate Timer Control Register must be set to the

correct value as shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode, a choice of internal clocks can be used as

the Timer/Event Counter clock. However, this clock

source is further divided by a prescaler, the value of

which is determined by the Prescaler Rate Select bits,

which are bits 0~2 in the respective Timer Control Reg-

ister. After the other bits in the Timer Control Register

have been setup, the enable bit, which is bit 4 of the

Timer Control Register, can be set high to enable the

Timer/Event Counter to run. Each time an internal clock

cycle occurs, the Timer/Event Counter increments by

one. When it is full and overflows, an interrupt signal is

generated and the Timer/Event Counter will reload the

value already loaded into the preload register and con-

tinue counting. The interrupt can be disabled by ensur-

ing that the Timer/Event Counter Interrupt Enable bit in

the Interrupt Control Register, is reset to zero.

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pins, can be re-

corded by the Timer/Event Counters. To operate in this

mode, the Operating Mode Select bit pair in the appro-

priate Timer Control Register must be set to the correct

value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode the external timer pins are used as the

Timer/Event Counter clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

appropriate Timer Control Register have been setup,

the enable bit, which is bit 4 of the Timer Control Regis-

ter, can be set high to enable the Timer/Event Counter to

run. If the Active Edge Select bit, which is bit 3 of the ap-

T M R C R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

E v e n t C o u n t e r A c t i v e E d g e S e l e c t

1 : c o u n t o n f a l l i n g e d g e

0 : c o u n t o n r i s i n g e d g e

b 7

T E

T O N

T M 0

T M 1

T i m e r P r e s c a l e r R a t e S e l e c t

b 0

P S C 0

P S C 1

P S C 2

P S C 0

T i m e r R a t e

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

1 : 2 5 6

T i m e r / E v e n t C o u n t e r C o u n t i n g E n a b l e

1 : e n a b l e

0 : d i s a b l e

O p e r a t i n g M o d e S e l e c t

T M 1

T M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

P u l s e W i d t h M e a s u r e m e n t A c t i v e E d g e S e l e c t

1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e

0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

P S C 2

P S C 1

Timer/Event Counter Control Register

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

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