HT46R92 datasheet(24/61 Pages) HOLTEK

24 / 61 page

HT46R92

Rev. 1.10

November 5, 2008

four sub-cycles contains 64 clock cycles. In this mode, a

modulation frequency increase by a factor of four is

achieved. The 8-bit PWM register value, which repre-

sents the overall duty cycle of the PWM waveform, is di-

vided into two groups. The first group which consists of

bit2~bit7 is denoted here as the DC value. The second

group which consists of bit0~bit1 is known as the AC

value. In the 6+2 PWM mode, the duty cycle value of

each of the four modulation sub-cycles is shown in the

following table.

Parameter

AC (0~3)

(Duty Cycle)

Modulation cycle i

(i=0~3)

i<AC

DC+1

³AC

6+2 Mode Modulation Cycle Values

The following diagram illustrates the waveforms associ-

ated with the 6+2 mode of PWM operation. It is impor-

tant to note how the single PWM cycle is subdivided into

4 individual modulation cycles, numbered from 0~3 and

how the AC value is related to the PWM value.

7+1 PWM Mode

Each full PWM cycle, as it is controlled by an 8-bit regis-

ter, has 256 clock periods. However, in the 7+1 PWM

mode, each PWM cycle is subdivided into two individual

sub-cycles known as modulation cycle 0 ~ modulation cy-

cle 1, denoted as

²i² in the table. Each one of these two

sub-cycles contains 128 clock cycles. In this mode, a

modulation frequency increase of two is achieved. The

8-bit PWM register value, which represents the overall

duty cycle of the PWM waveform, is divided into two

groups. The first group which consists of bit1~bit7 is de-

noted here as the DC value. The second group which

consists of bit0 is known as the AC value. In the 7+1

PWM mode, the duty cycle value of each of the two mod-

ulation sub-cycles is shown in the following table.

Parameter

AC (0~1)

(Duty Cycle)

Modulation cycle i

(i=0~1)

<AC

DC+1

128

³AC

128

7+1 Mode Modulation Cycle Values

The following diagram illustrates the waveforms associ-

ated with the 7+1 mode of PWM operation. It is impor-

tant to note how the single PWM cycle is subdivided into

2 individual modulation cycles, numbered 0 and 1 and

how the AC value is related to the PWM value.

PWM Output Control

PWM

Modulation

Frequency

PWM Cycle

Frequency

PWM Cycle

Duty

fSYS/64

fSYS/256

(PWM register

value)/256

The PWM0 output is shared with pin PA4, the PWM1

output is shared with PA5. To operate as a PWM output

and not as I/O pins, the correct PWM configuration op-

tion must be selected. A

²0² must also be written to the

corresponding bit in the I/O port control register, PAC.4

or PAC.5, to ensure that the corresponding PWM0 or

f S Y S / 2

P W M

[ P W M ] = 1 0 0

[ P W M ] = 1 0 1

P W M

[ P W M ] = 1 0 2

P W M

[ P W M ] = 1 0 3

P W M

P W M c y c l e : 2 5 6 / f S Y S

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

M o d u l a t i o n c y c l e 0

P W M m o d u l a t i o n p e r i o d : 6 4 / f S Y S

M o d u l a t i o n c y c l e 1

M o d u l a t i o n c y c l e 2

M o d u l a t i o n c y c l e 3

M o d u l a t i o n c y c l e 0

6+2 PWM Mode

P W M 0 , P W M 1 R e g i s t e r

b 7

b 0

A C v a l u e

D C v a l u e

6+2 Pulse Width Modulation Mode Registers

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