HT67F60 datasheet(61/242 Pages) HOLTEK

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HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

March 06 , 2012

Rev. 1.50

March 06 , 2012

● IDLE1 Mode

The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in

the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode

the system oscillator will be inhibited from driving the CPU but may continue to provide a clock

source to keep some peripheral functions operational such as the Watchdog Timer, TMs, LCD

driver, SPIA and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this

system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the

Watchdog Timer clock, fS, will be on. If the source is fSYS/4 then the fS clock will be on, and if the

source comes from fSUB then fS will be on.

Control Register

A single register, SMOD, is used for overall control of the internal clocks within the device.

●

SMOD Register

Bit

Name

CKS2

CKS1

CKS0

FSTEN

LTO

HTO

IDLEN

HLCLK

R/W

POR

Bit 7~5

CKS2~CKS0: The system clock selection when HLCLK is "0"

000: fL (fLXT or fLIRC)

001: fL (fLXT or fLIRC)

010: fH/64

011: fH/32

100: fH/16

101: fH/8

110: fH/4

111: fH/2

These three bits are used to select which clock is used as the system clock source. In

addition to the system clock source, which can be either the LXT or LIRC, a divided

version of the high speed system oscillator can also be chosen as the system clock

source.

Bit 4

FSTEN: Fast Wake-up Control (only for HXT)

0: Disable

1: Enable

This is the Fast Wake-up Control bit which determines if the fSUB clock source is

initially used after the device wakes up. When the bit is high, the fSUB clock source can

be used as a temporary system clock to provide a faster wake up time as the fSUB clock

is available.

Bit 3

LTO: Low speed system oscillator ready flag

0: Not ready

1: Ready

This is the low speed system oscillator ready flag which indicates when the low speed

system oscillator is stable after power on reset or a wake-up has occurred. The flag

will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will

change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2

clock cycles if the LIRC oscillator is used.

Bit 2

HTO: High speed system oscillator ready flag

0: Not ready

1: Ready

HT67F60 Datasheet(PDF) 61 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 61 Page - Holtek Semiconductor Inc

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