HT67F60 datasheet(138/242 Pages) HOLTEK

138 / 242 page

Rev. 1.50

138

March 06 , 2012

Rev. 1.50

139

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

Compare Output Mode

To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers

should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared

by three methods. These are a counter overflow, a compare match from Comparator A and a compare

match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter

can be cleared. One is when a compare match occurs from Comparator P, the other is when the

CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt

request flags for Comparator A and Comparator P respectively, will both be generated.

If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare

match occurs from Comparator A. However, here only the TnAF interrupt request flag will be

generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

TnCCLR is high no TnPF interrupt request flag will be generated.

As the name of the mode suggests, after a comparison is made, the TM output pin, will change state.

The TM output pin condition however only changes state when an TnAF or TnBF interrupt request

flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF

interrupt request flag, generated from a compare match from Comparator P, will have no effect on

the TM output pin. The way in which the TM output pin changes state is determined by the condition

of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and

TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the

TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or

TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match

occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of

the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the

TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the

TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place.

Counter Value

0x3FF

CCRP

CCRA

TnON

TnPAU

TnAPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TPnA O/P

Time

CCRP=0

CCRP > 0

Counter overflow

CCRP > 0

Counter cleared by CCRP value

Pause

Resume

Stop

Counter

Restart

TnCCLR = 0; TnAM [1:0] = 00

Output pin set to

initial Level Low

if TnAOC=0

Output Toggle with

TnAF flag

Note TnAIO [1:0] = 10

Active High Output select

Here TnAIO [1:0] = 11

Toggle Output select

Output not affected by TnAF

flag. Remains High until reset

by TnON bit

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Output Inverts

when TnAPOL is high

ETM CCRA Compare Match Output Mode — TnCCLR = 0

Note: 1. With TnCCLR=0 a Comparator P match will clear the counter

2. The TPnA output pin is controlled only by the TnAF flag

3. The output pin is reset to its initial state by a TnON bit rising edge

HT67F60 Datasheet(PDF) 138 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 138 Page - Holtek Semiconductor Inc

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