SC401B datasheet(25/32 Pages) SEMTECH

25 / 32 page

SC401B

Applications Information (continued)

Note that C

OUT is much smaller in this example, 169µF

compared to 316µF based on a worst-case load release. To

meet the two design criteria of minimum 316µF and

maximum 10.2mΩ ESR, select one capacitor of 330µF and

9mΩ ESR.

Electrolytic capacitors have parasitic inductance or equiv-

alent series inductance (ESL). This ESL increases the peak

to peak magnitude of the output voltage ripple. Therefore,

it is recommended that an additional small ceramic

capacitor be placed in parallel with C

OUT in order to filter

high frequency switching noise. As a result of the combi-

nation of the electrolytic capacitor’s ESL and the ceramic

capacitor, the output votlage ripple can take a resonant

form instead of the ideal triangle shape. If the ESL value is

high, it can cause cycle by cycle variation in the converter

switching frequency. The capacitor manufacturers usually

include the impedance vs frequency curve in their data-

sheets. For example, EEF-SX0E331ER from Panasonic or

4TPE220MF from Sanyo has typically 1.5nH at 10MHz.

Stability Considerations

Unstable operation is possible with adaptive on-time con-

trollers, and usually takes the form of double-pulsing or

ESR loop instability.

Double-pulsing occurs due to switching noise seen at the

FB input or because the FB ripple voltage is too low. This

causes the FB comparator to trigger prematurely after the

250ns minimum off-time has expired. In extreme cases

the noise can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect opera-

tion. This form of instability can usually be avoided by

providing the FB pin with a smooth, clean ripple signal

that is at least 10mVp-p, which may dictate the need to

increase the ESR of the output capacitors. It is also impera-

tive to provide a proper PCB layout as discussed in the

Layout Guidelines section.

Another way to eliminate doubling-pulsing is to add a

small (~ 10pF) capacitor across the upper feedback resis-

tor, as shown in Figure 12. This capacitor should be left

unpopulated until it can be confirmed that double-pulsing

exists. Adding the C

TOP capacitor will couple more ripple

into FB to help eliminate the problem. An optional con-

nection on the PCB should be available for this capacitor.

VOUT

To FB pin

CTOP

Figure 12 — Capacitor Coupling to FB Pin

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR

Requirements section. The best method for checking sta-

bility is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and

ringing. Ringing for more than one cycle after the initial

step is an indication that the ESR should be increased.

ESR Requirements

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide

10mVp-p at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insuffi-

cient ESR. The on-time control regulates the valley of the

output ripple voltage. This ripple voltage is the sum of the

two voltages. One is the ripple generated by the ESR, the

other is the ripple due to capacitive charging and dis-

charging during the switching cycle. For most applica-

tions the minimum ESR ripple voltage is dominated by the

output capacitors, typically SP or POSCAP devices. For

stability the ESR zero of the output capacitor should be

lower than approximately one-third the switching fre-

quency. The formula for minimum ESR is shown by the

following equation.

OUT

MIN

Using Ceramic Output Capacitors

When the system is using high ESR value capacitors, the

feedback voltage ripple lags the phase node voltage by 90

degrees. Therefore, the converter is easily stabilized.

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