ADSP-BF607 datasheet(16/44 Pages) AD

16 / 44 page

Rev. PrD

Page 16 of 44

March 2012

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Preliminary Technical Data

Clock Out/External Clock

The SYS_CLKOUT output pin has programmable options to

output divided-down versions of the on-chip clocks, including

USB clocks. Note that the USBCLK is provided for debug pur-

poses only and is not supported or guaranteed for clocking

customer applications. By default, the SYS_CLKOUT pin drives

a buffered version of the SYS_CLKIN input. Clock generation

faults (for example PLL unlock) may trigger a reset by hardware.

The clocks shown in Table 3 can be outputs from

SYS_CLKOUT.

Power Management

As shown in Table 4, the processor supports five different power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. There are no

sequencing requirements for the various power domains, but all

domains must be powered according to the appropriate Specifi-

cations table for processor operating conditions; even if the

feature/peripheral is not used.

The dynamic power management feature of the processor

allows the processor’s core clock frequency (fCCLK) to be dynam-

ically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor cores and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clocks and system clocks

run at the input clock (SYS_CLKIN) frequency. DMA access is

available to appropriately configured L1 memories.

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF60x Blackfin Pro-

cessor Hardware Reference.

See Table 5 for a summary of the power settings for each mode.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core and to all synchronous

peripherals. Asynchronous peripherals may still be running but

cannot access internal resources or external memory.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor cores and to all of the

peripherals. This setting signals the external voltage regulator

supplying the VDD_INT pins to shut off using the

SYS_EXTWAKE signal, which provides the lowest static power

dissipation. Any critical information stored internally (for

example, memory contents, register contents, and other infor-

mation) must be written to a non-volatile storage device prior to

removing power if the processor state is to be preserved.

Since the VDD_EXT pins can still be supplied in this mode, all of

the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

Reset Control Unit

Reset is the initial state of the whole processor or one of the

cores and is the result of a hardware or software triggered event.

In this state, all control registers are set to their default values

Table 3. Clock Dividers

Clock Source

Divider

CCLK (core clock)

By 4

SYSCLK (System clock)

By 2

SCLK0 (system clock for PVP, all

peripherals not covered by

SCLK1)

None

SCLK1 (system clock for SPORTS,

SPI, ACM)

None

DCLK (LPDDR/DDR2 clock)

By 2

OCLK (output clock)

Programmable

USBCLK

None

CLKBUF

None, direct from SYS_CLKIN

USBCLKBUF

None, direct from USB_CLKIN

Table 4. Power Domains

Power Domain

VDD Range

All internal logic

VDD_INT

DDR2/LPDDR

VDD_DMC

USB

VDD_USB

Thermal diode

VDD_TD

All other I/O (includes SYS, JTAG, and Ports pins) VDD_EXT

Table 5. Power Settings

Mode/State PLL

PLL

Bypassed fCCLK

fSYSCLK,

fDCLK,

fSCLK0,

fSCLK1

Core

Power

Full On

Enabled

Enabled Enabled

Active

Enabled/

Disabled

Yes

Enabled Enabled

Deep Sleep

Disabled —

Disabled Disabled

Hibernate

Disabled —

Disabled Disabled

Off

ADSP-BF607 Datasheet(PDF) 16 Page - Analog Devices

ADSP-BF607 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL