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ADSP-BF607 Datasheet(PDF) 24 Page - Analog Devices

Part # ADSP-BF607
Description  Blackfin Dual Core
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF607 Datasheet(HTML) 24 Page - Analog Devices

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Rev. PrD
|
Page 24 of 44
|
March 2012
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 Preliminary Technical Data
PIN TERMINATION AND DRIVE CHARACTERISTICS-REQUIREMENTS
Table 8 identifies how each signal on the chip is internally ter-
minated and driven. In addition, external termination
requirements are provided. In this table the following columns
are used.
• Internal Termination – Specifies the termination present
when the processor is not in the reset or hibernate state.
• Reset Termination – Specifies the termination present
when the processor is in the reset state.
• Reset Drive – Specifies the active drive on the signal when
the processor is in the reset state.
• Hibernate Termination – Specifies the termination present
when the processor is in the hibernate state.
• Hibernate Drive – Specifies the active drive on the signal
when the processor is in the hibernate state.
• Notes – Specifies any special requirements or characteris-
tics for the signal. If no special requirements are listed the
signal may be left unconnected if it is not used.
Table 8. ADSP-BF60x Pad Table
Signal Name
Internal
Termination
Reset
Termination
Reset Drive Hibernate
Termination
Hibernate
Drive
Notes
DMC0_A00
None
None
None
None
None
No notes
DMC0_A01
None
None
None
None
None
No notes
DMC0_A02
None
None
None
None
None
No notes
DMC0_A03
None
None
None
None
None
No notes
DMC0_A04
None
None
None
None
None
No notes
DMC0_A05
None
None
None
None
None
No notes
DMC0_A06
None
None
None
None
None
No notes
DMC0_A07
None
None
None
None
None
No notes
DMC0_A08
None
None
None
None
None
No notes
DMC0_A09
None
None
None
None
None
No notes
DMC0_A10
None
None
None
None
None
No notes
DMC0_A11
None
None
None
None
None
No notes
DMC0_A12
None
None
None
None
None
No notes
DMC0_A13
None
None
None
None
None
No notes
DMC0_BA0
None
None
None
None
None
No notes
DMC0_BA1
None
None
None
None
None
No notes
DMC0_BA2
None
None
None
None
None
For LPDDR leave unconnected.
DMC0_CAS
None
None
None
None
None
No notes
DMC0_CK
None
None
Low
None
Low
No notes
DMC0_CK
None
None
Low
None
Low
No notes
DMC0_CKE
None
None
Low
None
Low
No notes
DMC0_CS0
None
None
None
None
None
No notes
DMC0_DQ00
None
None
None
None
None
No notes
DMC0_DQ01
None
None
None
None
None
No notes
DMC0_DQ02
None
None
None
None
None
No notes
DMC0_DQ03
None
None
None
None
None
No notes
DMC0_DQ04
None
None
None
None
None
No notes
DMC0_DQ05
None
None
None
None
None
No notes
DMC0_DQ06
None
None
None
None
None
No notes
DMC0_DQ07
None
None
None
None
None
No notes
DMC0_DQ08
None
None
None
None
None
No notes
DMC0_DQ09
None
None
None
None
None
No notes
DMC0_DQ10
None
None
None
None
None
No notes
DMC0_DQ11
None
None
None
None
None
No notes



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