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ADSP-BF607 Datasheet(PDF) 19 Page - Analog Devices |
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ADSP-BF607 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 44 page  Preliminary Technical Data Rev. PrD | Page 19 of 44 | March 2012 ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 SIGNAL DESCRIPTIONS The processors’ signal definitions are shown in Table 6. Table 6. Processor Signal Descriptions Signal Name Function Driver Type Power Domain Ports Pins PA00 – PA15 Port A 00 – Port A 15 A VDD_EXT PB00 – PB15 Port B 00 – Port B 15 A VDD_EXT PC00 – PC15 Port C 00 – Port C 15 A VDD_EXT PD00 – PD15 Port D 00 – Port D 15 A VDD_EXT PE00 – PE15 Port E 00 – Port E 15 A VDD_EXT PF00 – PF15 Port F 00 – Port F 15 A VDD_EXT PG00 – PG15 Port G 00 – Port G 15 A VDD_EXT Dynamic Memory Controller DMC0_A00 – DMC0_A13 DMC0 Address 0 – DMC0 Address 13 B VDD_DMC DMC0_BA0 DMC0 Bank Address Input 0 B VDD_DMC DMC0_BA1 DMC0 Bank Address Input 1 B VDD_DMC DMC0_BA2 DMC0 Bank Address Input 2 B VDD_DMC DMC0_CAS DMC0 Column Address Strobe B VDD_DMC DMC0_CK DMC0 Clock C VDD_DMC DMC0_CK DMC0 Clock (complement) C VDD_DMC DMC0_CKE DMC0 Clock enable B VDD_DMC DMC0_CS0 DMC0 Chip Select 0 B VDD_DMC DMC0_DQ00 – DMC0_DQ15 DMC0 Data 0 – DMC0 Data 15 B VDD_DMC DMC0_LDM DMC0 Data Mask for Lower Byte B VDD_DMC DMC0_LDQS DMC0 Data Strobe for Lower Byte C VDD_DMC DMC0_LDQS DMC0 Data Strobe for Lower Byte (complement) C VDD_DMC DMC0_ODT DMC0 On-die termination B VDD_DMC DMC0_RAS DMC0 Row Address Strobe B VDD_DMC DMC0_UDM DMC0 Data Mask for Upper Byte B VDD_DMC DMC0_UDQS DMC0 Data Strobe for Upper Byte C VDD_DMC DMC0_UDQS DMC0 Data Strobe for Upper Byte (complement) C VDD_DMC DMC0_WE DMC0 Write Enable B VDD_DMC JTAG Test Access Port JTG_EMU JTG Emulation Output A VDD_EXT JTG_TCK JTG Clock VDD_EXT JTG_TDI JTG Serial Data In VDD_EXT JTG_TDO JTG Serial Data Out A VDD_EXT JTG_TMS JTG Mode Select VDD_EXT JTG_TRST JTG Reset VDD_EXT Static Memory Controller SMC0_A01 SMC0 Address 1 A VDD_EXT SMC0_A02 SMC0 Address 2 A VDD_EXT SMC0_AMS0 SMC0 Memory Select 0 A VDD_EXT SMC0_AOE/SMC0_NORDV SMC0 Output Enable/SMC0 NOR Data Valid A VDD_EXT SMC0_ARDY/SMC0_NORWT SMC0 Asynchronous Ready/SMC0 NOR Wait VDD_EXT SMC0_ARE SMC0 Read Enable A VDD_EXT SMC0_AWE SMC0 Write Enable A VDD_EXT SMC0_BR SMC0 Bus Request VDD_EXT SMC0_D00 – SMC0_D15 SMC0 Data 0 – SMC0 Data 15 A VDD_EXT |
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