ADSP-BF607 datasheet(23/44 Pages) AD

23 / 44 page

Preliminary Technical Data

Rev. PrD

Page 23 of 44

March 2012

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609

PG_02/ETH1_TXD1/PWM1_AL/RSI0_D1

PG Position 2/ETH1 Transmit Data 1/PWM1 Channel A Low Side/RSI0 Data 1

PG_03/ETH1_TXD0/PWM1_AH/RSI0_D0

PG Position 3/ETH1 Transmit Data 0/PWM1 Channel A High Side/RSI0 Data 0

PG_04/SPT2_ACLK/TM0_TMR1/CAN0_RX/

TM0_ACI2

PG Position 4/SPORT2 Channel A Clock/TIMER0 Timer 1/CAN0 Receive/

TIMER0 Alternate Capture Input 2

PG_05/ETH1_TXEN/RSI0_CMD/PWM1_SYNC/

ACM0_T1

PG Position 5/ETH1 Transmit Enable/RSI0 Command/PWM1 Sync/

ACM0 External Trigger 1

PG_06/ETH1_REFCLK/RSI0_CLK/SPT2_BTDV/

PWM1_TRIP0

PG Position 6/ETH1 Reference Clock/RSI0 Clock/SPORT2 Channel B Transmit Data Valid/

PWM1 Shutdown Input 0

PG_07/SPT2_BFS/TM0_TMR5/CNT0_ZM

PG Position 7/SPORT2 Channel B Frame Sync/ TIMER0 Timer 5/CNT0 Count Zero Marker

PG_08/SPT2_AD1/TM0_TMR3/PWM1_TRIP1

PG Position 8/SPORT2 Channel A Data 1/TIMER0 Timer 3/PWM1 Shutdown Input

PG_09/SPT2_AD0/TM0_TMR4

PG Position 9/SPORT2 Channel A Data 0/TIMER0 Timer 4

PG_10/UART1_RTS/SPT2_BCLK

PG Position 10/UART1 Request to Send/SPORT2 Channel B Clock

PG_11/SPT2_BD1/TM0_TMR6/CNT0_UD

PG Position 11/SPORT2 Channel B Data 1/TIMER0 Timer 6/CNT0 Count Up and Direction

PG_12/SPT2_BD0/TM0_TMR7/CNT0_DG

PG Position 12/SPORT2 Channel B Data 0/TIMER0 Timer 7/CNT0 Count Down and Gate

PG_13/UART1_CTS/TM0_CLK

PG Position 13/UART1 Clear to Send/TIMER0 Clock

PG_14/UART1_RX/SYS_IDLE1/TM0_ACI1

PG Position 14/UART1 Receive/SYS Core 1 Idle Indicator/TIMER0 Alternate Capture Input 1

PG_15/UART1_TX/SYS_IDLE0/SYS_SLEEP/

TM0_ACI4

PG Position 15/UART1 Transmit/SYS Core 0 Idle Indicator/SYS Processor Sleep Indicator/

TIMER0 Alternate Capture Input 4

Table 7. Processor Multiplexing Scheme (Continued)

Signal Name

Function

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