DM9106 datasheet(2/92 Pages) DAVICOM

2 / 92 page

DM9106

3-port switch with PCI Interface

Preliminary datasheet

DM9106-DS-P01

July 9, 2009

GENERAL DESCRIPTION............................................................................................... 8

BLOCK DIAGRAM........................................................................................................... 8

FEATURES ...................................................................................................................... 9

PIN CONFIGURATION : 128 PIN LQFP........................................................................ 10

PIN DESCRIPTION ........................................................................................................ 11

5.1 PCI BUS INTERFACE ...................................................................................................................................... 11

5.2 P2 MII / RMII / REVERSE MII INTERFACES...................................................................................................... 12

5.2.1 MII Interfaces ....................................................................................................................................... 12

5.2.2 RMII Interfaces..................................................................................................................................... 13

5.2.3 Reverse MII Interfaces......................................................................................................................... 13

5.3 EEPROM INTERFACES ................................................................................................................................. 13

5.4 LED PINS ..................................................................................................................................................... 14

5.5 CLOCK INTERFACE ........................................................................................................................................ 14

5.6 NETWORK INTERFACE.................................................................................................................................... 14

5.7 MISCELLANEOUS PINS ................................................................................................................................... 15

5.8 POWER PINS ................................................................................................................................................. 15

5.9 STRAP PINS TABLE ........................................................................................................................................ 16

5.9.1 Strap pin in 3-port mode ...................................................................................................................... 16

DESCRIPTION ...................................................................................................................................................... 16

5.9.2 strap pin in 2-port mode....................................................................................................................... 17

DESCRIPTION ...................................................................................................................................................... 17

REGISTER SET ............................................................................................................. 18

6.1 PCI CONFIGURATION REGISTERS................................................................................................................... 18

6.1.1 Identification ID (xxxxxx00H - PCIID) .................................................................................................. 19

6.1.2 Command & Status (xxxxxx04H - PCICS) .......................................................................................... 19

6.1.3 Revision ID (xxxxxx08H - PCIRV) ....................................................................................................... 20

6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT) ..................................................................................... 21

6.1.5 I/O Base Address (xxxxxx10H - PCIIO)............................................................................................... 21

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