DM9106 datasheet(28/92 Pages) DAVICOM

28 / 92 page

DM9106

3-port switch with PCI Interface

Preliminary datasheet

DM9106-DS-P01

July 9, 2009

Move data from receive FIFO to host memory

Close descriptor by clearing owner bit of descriptor

Close descriptor by writing status

Receive process suspended due to buffer unavailable

Purge the current frame from received FIFO

because of the unavailable received buffer

NIS

0,RW

Normal Interrupt Summary

Normal interrupt includes any of the three conditions:

CR5<0> – TXCI: Transmit Complete Interrupt

CR5<2> – TXDU: Transmit Buffer Unavailable

CR5<6> – RXCI: Receive Complete Interrupt

AIS

0,RW

Abnormal Interrupt Summary

Abnormal interrupt includes any interrupt condition as shown below, excluding

Normal Interrupt conditions. They are TXPS (bit1), TXFU (bit5), RXDU (bit7), RXPS

(bit8), SBE (bit13).

RESERVED

0,RW

Reserved

SBE

0,RW

System Bus Error

The PCI system bus errors will set this bit. The type of system bus error is shown in

CR5<25:23>.

LINKS

0,RO

Link Change Status

This bit is set to indicate that the link status changed in port 0 or 1 PHYceiver

RESERVED

0,RO

Reserved

10:9

RESERVED

0,RO

Reserved

RXPS

0,RW

Receive Process Stopped

This bit is set to indicate that the receive process enters the stopped state.

RXDU

0,RW

Receive Buffer Unavailable

This bit is set when the DM9106 fetches the next receive descriptor that is still owned

by the host. Receive process will be suspended until a new frame enters or the

receive polling command is set.

RXCI

0,RW

Receive Complete Interrupt

This bit is set when a received frame is fully moved into host memory and receive

status has been written to descriptor. Receive process is still running and continues to

fetch next descriptor.

TXFU

0,RW

Transmit FIFO Underrun

This bit is set when transmit FIFO has underrun condition during the packet

transmission. It may happen due to the heavy load on bus, cause transmit buffer

unavailable before end of packet. In this case, transmit process is placed in the

suspend state and underrun error TDES0<1> is set.

RESERVED

0,RO

Reserved

RESERVED

0,RO

Reserved

TXDU

0,RW

Transmit Buffer Unavailable

This bit is set when the DM9106 fetches the next transmit descriptor that is still owned

by the host. Transmit process will be suspended until the transmission polling

command is set.

TXPS

0,RW

Transmit Process Stopped

This bit is set to indicate transmit process enters the stopped state.

TXCI

0,RW

Transmit Complete Interrupt

This bit is set when a frame is fully transmitted and transmit status has been written to

descriptor (the TDES1<31> is also asserted). Transmit process is still running and

continues to fetch next descriptor.

DM9106 Datasheet(PDF) 28 Page - Davicom Semiconductor, Inc.

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