DM9106 datasheet(21/92 Pages) DAVICOM

21 / 92 page

DM9106

3-port switch with PCI Interface

Preliminary datasheet

DM9106-DS-P01

July 9, 2009

6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT)

Bit

Default

Type

Description

31:24

00H

Built In Self Test ( 00H means No Implementation)

23:16

00H

Header Type ( 00H means single function with Predefined Header Type ).

15:8

00H

Latency Timer For The Bus Master

The latency timer is guaranteed by the system and measured by clock cycles.

When the FRAME# is asserted at the beginning of a master period by the

DM9106, the value will be copied into a counter and start counting down. If the

FRAME# is de-asserted prior to count expiration, this value is meaningless. When

the count expires before GNT# is de-asserted, the master transaction will be

terminated as soon as the GNT# is removed

While GNT# signal is removed and the counter is non-zero, the DM9106 will

continue with its data transfers until the count expires. The system host will read

MIN_GNT and MAX_LAT registers to determine the latency requirement for the

device and then initialize the latency timer with an appropriate value

The reset value of Latency Timer is determined by BIOS

7:0

00H

Cache Line Size For Memory Read Mode Selection ( 00H means No

Implementation For Use)

6.1.5 I/O Base Address (xxxxxx10H - PCIIO)

Bit

Default

Type

Description

31:7

Undefined

PCI I/O Base Address

This is the base address value for I/O accesses cycles. It will be compared to

AD[31:7] in the address phase of bus command cycle for the I/O resource access

6:1

000000

PCI I/O Range Indication

It indicates that the minimum I/O resource size is 80h

I/O Space Or Memory Space Base Indicator

Determines that the register maps into the I/O space ( = 1 Indicates I/O Base)

6.1.6 Memory Mapped Base Address (xxxxxx14H - PCIMEM)

Bit

Default

Type

Description

31:7

Undefined

R/W

PCI Memory Base Address

This is the base address value for memory accesses cycles. It will be compared to

the AD [31:7] in the address phase of bus command cycle for the Memory resource

access

6:1

000000

PCI Memory Range Indication

It indicates that the minimum memory resource size is 80h

I/O Space Or Memory Space Base Indicator

Determines that the register maps into the memory space( = 0 Indicates Memory

Base)

DM9106 Datasheet(PDF) 21 Page - Davicom Semiconductor, Inc.

DM9106 Datasheet(HTML) 21 Page - Davicom Semiconductor, Inc.

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