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MK30DX64VMB7 Datasheet(PDF) 70 Page - Freescale Semiconductor, Inc |
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MK30DX64VMB7 Datasheet(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 72 page ![]() 1 A PTD7 B NC C NC D NC E NC F PTE16 G PTE18 H NC J NC K PGA0_DP/ 1 L PGA1_DP/ 2 PTD5 PTD6/ NC NC PTE2/ PTE17 PTE19 NC NC PGA0_DM/ 2 PGA1_DM/ 3 PTD4/ PTD3 PTD2/ PTD1 PTE1/ NC VSS NC NC NC 3 VREF_OUT/ 4 NC NC NC PTD0/ PTE0 PTE3 PTE5 NC NC NC 4 XTAL32 5 NC NC PTC11/ NC VDD VDDA VREFH NC NC DAC0_OUT/ 5 EXTAL32 6 NC NC PTC10 PTC9 VDD VSSA VREFL NC PTA0 VBAT 6 VSS 7 PTC8 PTC7 PTC6/ PTC5/ VDD VSS VSS PTE4/ PTA2 PTA5 7 RTC_ 8 PTC4/ PTC3/ PTC2 PTC1/ NC NC PTB3 PTA1 PTA4/ PTA12 8 PTA13/ 9 VLL1 PTC0 PTB19 PTB18 PTB17 NC PTB2 PTA3 NC PTA14 9 PTA15 10 VLL2 PTB16 PTB11 PTB10 PTB9 NC PTB1 PTA17 PTA16 VSS 10 VDD 11 A VLL3 B VCAP2 C VCAP1 D PTB8 E NC F NC G PTB0/ H NC J RESET_b K PTA19 11 L PTA18 LLWU_P14 LLWU_P8 LLWU_P15 LLWU_P7 LLWU_P13 LLWU_P11 LLWU_P10 LLWU_P12 LLWU_P9 LLWU_P6 LLWU_P1 LLWU_P0 LLWU_P5 LLWU_P2 LLWU_P3 CMP1_IN3/ ADC0_SE23 ADC0_DM0/ ADC1_DM3 ADC0_DP0/ ADC1_DP3 CMP1_IN5/ CMP0_IN5/ ADC1_SE18 ADC1_DM0/ ADC0_DM3 ADC1_DP0/ ADC0_DP3 WAKEUP_B LLWU_P4 Figure 28. K30 81 MAPBGA Pinout Diagram 9 Revision History The following table provides a revision history for this document. Table 45. Revision History Rev. No. Date Substantial Changes 1 3/2012 Initial public release Table continues on the next page... Revision History K30 Sub-Family Data Sheet, Rev. 2, 4/2012. 70 Freescale Semiconductor, Inc. |
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