AFE8220TPZPQ1 datasheet(32/49 Pages) TI1

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Alternate Registers—GPIO and Input Attenuator

Interrupt Generators

AFE8220-Q1

SBAS455A – JANUARY 2009 – REVISED JULY 2009....................................................................................................................................................... www.ti.com

Table 17. General RTC Control Register

Settings (continued)

PARAMETER

ADDRESS

BITS

rtc_hours[5:0]

5:0

rtc_max_count[15:0]

15:0

rtc_minutes[6:0]

6:0

rtc_mode

rtc_month[4:0]

4:0

rtc_seconds[6:0]

6:0

rtc_year[7:0]

7:0

Table 18. GPIO Control Register Settings

PARAMETER

ADDRESS

BITS

gpio

11:0

gpio_delay[15:0]

15:0

gpio_oe

11:0

If some of the GPIO pins on the AFE8220 are to be used to control the gain of a tuner, it may be desirable to

change the GPIO values at the same time as the input attenuation to the DDC. To make this process more

deterministic, the control parameters gpio, ddc0_atten, and ddc1_atten can be accessed through the alternate

control register addresses of 96 and 97. By writing to register 96, gpio and ddc0_atten can be changed in a

single register write; by writing to register 97, gpio and ddc1_atten can be changed in a single register write.

Table 19 shows the operation control settings for these parameters.

Table 19. Alternate GPIO and DDC Control Register

Settings

PARAMETER

ADDRESS

BITS

gpio

7:0

ddc0_atten

14:12

ddc1_atten

There are three programmable interrupt pins; IRQ0, IRQ1, and IRQ2. Only the operation of IRQ0 is described

here; IRQ1 and IRQ2 are programmed in the same way, using different control variables.

Interrupts can be generated from various sources. Interrupt generation is enabled through irq0_en, as Table 20

shows.

Table 20. Interrupt Generation

BIT POSITION

SOURCE

BIT POSITION

SOURCE

GPIO

RTC alarm

None

RTC seconds rollover

I2C Master done

RTC minutes rollover

Aux ADC done

RTC hours rollover

IFADC0 over-range

RTC months rollover

IFADC1 over-range

RTC day rollover

IFADC0 limit

RTC year rollover

IFADC1 limit

—

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