AFE8220TPZPQ1 datasheet(12/49 Pages) TI1

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DETAILED DESCRIPTION

Reset Pins

Analog Supply Connections

Digital Supply Connections

External 1.8-V Core Supply

Internal 1.8-V Regulator

AFE8220-Q1

SBAS455A – JANUARY 2009 – REVISED JULY 2009....................................................................................................................................................... www.ti.com

The AFE8220 has two active-low reset pins, GRST and RST. When GRST is brought low, all registers on the

chip are brought to default values (0, unless otherwise specified). When RST is brought low, all registers are

brought to default values except for:

• Real-time clock registers (counters and alarms)

• Registers to configure the WAKEUP interrupt

• Registers controlling the GPIO pins

These registers are left in the previously programmed states.

A clean 3.3-V analog supply should be connected to all AVDD pins (26–27, 29, 38, 88, 97, and 99–100). Limited

decoupling is required on the AVDD pins; a 0.1-mF capacitor near pins 29 and 38 and another capacitor near

pins 88 and 97 should suffice.

The AFE8220 contains an internal analog switch that is used to disconnect power from the major analog blocks

when the PWD pin is high. When the PWD pin is low, the AVDD1 pins (1, 5, 6, 15, 16, and 25) are internally

connected to the AVDD pins (26, 27, 99, and 100). Because the AVDD1 pins are actually the active supply pins

for the IF ADC and other analog components, the AVDD1 pins should be heavily bypassed with a minimum of

parallel 0.1-

µF and 0.01-µF ceramic capacitors at each pin (or pin pair).

The digital supply connections depend on whether the onboard regulators are used to generate the 1.8-V digital

core voltage (REG_ENB low); or if the digital core voltage comes from a system-level supply (REG_ENB high).

In either case, all IOVDD pins should be connected to the 3.3-V IO supply and appropriately bypassed. If the

internal regulators are used, this supply also sources the current drawn by the digital core.

If an external 1.8-V supply is used, all DVDD pins should be connected to the 1.8-V supply and appropriately

bypassed with 0.1-

µF and 0.01-µF capacitors. DVDD1 and DVDD2 pins may also be connected directly to the

1.8-V supply or may be optionally connected through a small (1

Ω to 10 Ω) series resistor to reduce supply noise

coupling into the MCLK oscillator (powered through DVDD1) or the RTC oscillator (powered through DVDD2).

When using an external supply, the PWD pin disables the MCLK oscillator when high, shutting off the clock to

most of the digital core. As long as the external 1.8-V supply is maintained, all register settings in the digital core

are maintained with PWD is high.

If the internal 1.8-V regulator is used, then 0.1-

µF and 0.01-µF decoupling capacitors should still be put at the

DVDD, DVDD1, and DVDD2 pins. DVDD2 should still be connected to the DVDD pins either directly or through a

small series resistor. DVDD1 must be isolated from DVDD and DVDD2.

While using the internal regulators, the MCLK oscillator and the internal regulators are disabled when the PWD

pin is high. This condition causes most of the register settings to be lost, except for the registers associated with

the real-time clock, GPIO, and WAKEUP interrupt. For this reason, the RST pin should be brought low prior to

bringing the PWD pin low (to come out of power-down). The RST pin should be held low for at least 10 ms after

PWD goes low to allow the internal regulators to stabilize.

Note that the internal regulators are linear regulators, and therefore are relatively inefficient. Power dissipation as

a result of the digital core almost doubles when the internal regulators are used (same core current, but drawn

from a 3.3-V supply instead of a 1.8-V supply). Whenever possible, the use of a more efficient external switching

regulator is encouraged in order to minimize overall system power as well as to reduce the thermal stress on the

AFE8220.

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